Patents by Inventor James Anthony Marcella
James Anthony Marcella has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7873773Abstract: A circuit arrangement, method and apparatus utilize communication links that are selectively configurable to operate in both unidirectional and bidirectional modes to communicate data between multiple nodes that are interconnected to one another in a daisy chain configuration. As a result, in many instances communications may be maintained with nodes located both before and after a discontinuity in a daisy chain configuration.Type: GrantFiled: April 26, 2007Date of Patent: January 18, 2011Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, John Michael Borkenhagen, Robert Allen Drehmel, James Anthony Marcella
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Patent number: 7802158Abstract: A diagnostic interface architecture for a memory device supports in one aspect one or more dynamically reconfigurable functional interconnects normally utilized in connection with reading data from the memory device and/or writing data to the memory device. The dynamically reconfigurable functional interconnects are capable of being configured to operate in either functional or diagnostic modes, whereby in the diagnostic mode, such interconnects may be used to communicate diagnostic information to support one or more diagnostic operations. The diagnostic interface architecture may also support multiple diagnostic interfaces in a given memory device, with at least one such diagnostic interface being capable of being selectively enabled in response to a failure in another diagnostic interface.Type: GrantFiled: March 23, 2009Date of Patent: September 21, 2010Assignee: International Business Machines CorporationInventors: John Michael Borkenhagen, William Paul Hovis, James Anthony Marcella, Paul Rudrud
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Publication number: 20090183039Abstract: A diagnostic interface architecture for a memory device supports in one aspect one or more dynamically reconfigurable functional interconnects normally utilized in connection with reading data from the memory device and/or writing data to the memory device. The dynamically reconfigurable functional interconnects are capable of being configured to operate in either functional or diagnostic modes, whereby in the diagnostic mode, such interconnects may be used to communicate diagnostic information to support one or more diagnostic operations. The diagnostic interface architecture may also support multiple diagnostic interfaces in a given memory device, with at least one such diagnostic interface being capable of being selectively enabled in response to a failure in another diagnostic interface.Type: ApplicationFiled: March 23, 2009Publication date: July 16, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Michael Borkenhagen, William Paul Hovis, James Anthony Marcella, Paul Rudrud
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Patent number: 7526692Abstract: A diagnostic interface architecture for a memory device supports in one aspect one or more dynamically reconfigurable functional interconnects normally utilized in connection with reading data from the memory device and/or writing data to the memory device. The dynamically reconfigurable functional interconnects are capable of being configured to operate in either functional or diagnostic modes, whereby in the diagnostic mode, such interconnects may be used to communicate diagnostic information to support one or more diagnostic operations. The diagnostic interface architecture may also support multiple diagnostic interfaces in a given memory device, with at least one such diagnostic interface being capable of being selectively enabled in response to a failure in another diagnostic interface.Type: GrantFiled: September 30, 2004Date of Patent: April 28, 2009Assignee: International Business Machines CorporationInventors: John Michael Borkenhagen, William Paul Hovis, James Anthony Marcella, Paul Rudrud
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Patent number: 7254663Abstract: A circuit arrangement, method and apparatus utilize communication links that are selectively configurable to operate in both unidirectional and bidirectional modes to communicate data between multiple nodes that are interconnected to one another in a daisy chain configuration. As a result, in many instances communications may be maintained with nodes located both before and after a discontinuity in a daisy chain configuration.Type: GrantFiled: July 22, 2004Date of Patent: August 7, 2007Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, John Michael Borkenhagen, Robert Allen Drehmel, James Anthony Marcella
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Patent number: 7234017Abstract: A high speed computer processor system has a high speed interface for a graphics processor. A preferred embodiment combines a PowerPC microprocessor called the Giga-Processor Ultralite (GPUL) 110 from International Business Machines Corporation (IBM) with a high speed interface on a multi-chip module.Type: GrantFiled: February 24, 2005Date of Patent: June 19, 2007Assignee: International Business Machines CorporationInventors: Giora Biran, Matthew Adam Cushing, Robert Allen Drehmel, Allen James Gavin, Mark E. Kautzman, Jamie Randall Kuesel, Ming-I Mark Lin, David Arnold Luick, James Anthony Marcella, Mark Owen Maxson, Eric Oliver Mejdrich, Adam James Muff, Clarence Rosser Ogilvie, Charles S. Woodruff
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Patent number: 6963516Abstract: A method and apparatus is provided which dynamically alters SDRAM memory interface timings to provide minimum read access latencies for different types of memory accesses in a memory subsystem of a computer system. The dynamic alteration of the SDRAM memory interface timings is based on workload and is determined with information from the memory controller read queue.Type: GrantFiled: November 27, 2002Date of Patent: November 8, 2005Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, John Michael Borkenhagen, Joseph Allen Kirscht, James Anthony Marcella, David Alan Shedivy
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Patent number: 6940760Abstract: A circuit arrangement and method are used in connection with a data latch that is coupled to a data source over a source synchronous communications interface to disable the data latch from latching data whenever the data source is not driving the source synchronous data strobe signal. As such, when the data source is not driving the source synchronous data strobe signal, undesired and/or inadvertent latching by the data latch can be avoided. Moreover, in implementations where a data strobe signal line is bidirectional, and capable of being driven either by the data source or by another circuit used to access the data source (e.g., a memory controller), disabling data latching as described herein can minimize the risk of driver damage resulting from conflicting attempts to drive the data strobe signal line at both ends.Type: GrantFiled: September 12, 2003Date of Patent: September 6, 2005Assignee: International Business Machines CorporationInventors: John Michael Borkenhagen, Todd Alan Greenfield, James Anthony Marcella
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Patent number: 6895482Abstract: An improved computer memory subsystem determines the most efficient memory command to execute. The physical location and any address dependency of each incoming memory command to a memory controller is ascertained and that information accompanies the command for categorization into types of command. For each type of memory command, there exists a command FIFO and associated logic in which a programmable number of the memory commands are selected for comparison with each other, with the memory command currently executing, and with the memory command previously chosen for execution. The memory command having the least memory cycle performance penalty is selected for execution unless that memory command has an address dependency. If more than one memory command of that type has the least memory cycle performance penalty, then the oldest is selected for execution.Type: GrantFiled: September 10, 1999Date of Patent: May 17, 2005Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Robert Allen Drehmel, Kent Harold Haselhorst, James Anthony Marcella
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Patent number: 6760856Abstract: A programmable compensated delay for a double data rate (DDR) synchronous dynamic random access memory (SDRAM) interface is provided. A programmable compensated delay apparatus includes a reference delay calibration circuit for providing a measured number of delay elements in one cycle. A programmable delay register provides a desired delay value. A conversion logic is coupled to the reference delay calibration circuit and the programmable delay register for receiving both the measured number of delay elements in one cycle and the desired delay value. The conversion logic provides a number of required delay elements. A delay circuit is coupled to the conversion logic for receiving the number of required delay elements and providing the desired delay. A SDRAM control logic provides a refresh start signal to the reference delay calibration circuit for updating the delay circuit during each DRAM refresh. The DQS clock strobe on the DDR SDRAM is applied to the delay circuit and is delayed by the desired delay.Type: GrantFiled: July 17, 2000Date of Patent: July 6, 2004Assignee: International Business Machines CorporationInventors: John Michael Borkenhagen, James Anthony Marcella
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Publication number: 20040103258Abstract: A method and apparatus is provided which dynamically alters SDRAM memory interface timings to provide minimum read access latencies for different types of memory accesses in a memory subsystem of a computer system. The dynamic alteration of the SDRAM memory interface timings is based on workload and is determined with information from the memory controller read queue.Type: ApplicationFiled: November 27, 2002Publication date: May 27, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Herman Lee Blackmon, John Michael Borkenhagen, Joseph Allen Kirscht, James Anthony Marcella, David Alan Shedivy
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Publication number: 20040071015Abstract: A circuit arrangement and method are used in connection with a data latch that is coupled to a data source over a source synchronous communications interface to disable the data latch from latching data whenever the data source is not driving the source synchronous data strobe signal. As such, when the data source is not driving the source synchronous data strobe signal, undesired and/or inadvertent latching by the data latch can be avoided. Moreover, in implementations where a data strobe signal line is bidirectional, and capable of being driven either by the data source or by another circuit used to access the data source (e.g., a memory controller), disabling data latching as described herein can minimize the risk of driver damage resulting from conflicting attempts to drive the data strobe signal line at both ends.Type: ApplicationFiled: September 12, 2003Publication date: April 15, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Michael Borkenhagen, Todd Alan Greenfield, James Anthony Marcella
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Patent number: 6671211Abstract: A circuit arrangement and method are used in connection with a data latch that is coupled to a data source over a source synchronous communications interface to disable the data latch from latching data whenever the data source is not driving the source synchronous data strobe signal. As such, when the data source is not driving the source synchronous data strobe signal, undesired and/or inadvertent latching by the data latch can be avoided. Moreover, in implementations where a data strobe signal line is bidirectional, and capable of being driven either by the data source or by another circuit used to access the data source (e.g., a memory controller), disabling data latching as described herein can minimize the risk of driver damage resulting from conflicting attempts to drive the data strobe signal line at both ends.Type: GrantFiled: April 17, 2001Date of Patent: December 30, 2003Assignee: International Business Machines CorporationInventors: John Michael Borkenhagen, Todd Alan Greenfield, James Anthony Marcella
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Patent number: 6628662Abstract: A method and system for arbitrating data transfers between devices connected via electronically isolated buses at a switch. In accordance with the method and system of the present invention, multiple arbitration controllers are interposed between devices and a switch to which the devices are connected, wherein each of the multiple arbitration controllers are effective to select a data transfer operation and detect collisions between said selected data transfer operations. The switch is enabled for any selected data transfer operations between which collisions are not detected. The switch is also enabled for only one of the selected data transfer operations between which collisions are detected. Any selected data transfer operations for which the switch is not enabled are deferred.Type: GrantFiled: November 29, 1999Date of Patent: September 30, 2003Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Robert Allen Drehmel, Kent Harold Haselhorst, James Anthony Marcella
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Patent number: 6557069Abstract: An internal processor/memory bus contains an address portion for transmitting addresses and commands, having a series of hierarchical uni-directional links between processors and local repeaters (ARPs), and between the ARPs and a central repeater (ASW). A command propagates from a requesting device to its local ARP, to the ASW. From the ASW, the command is broadcast to all devices on the bus by transmitting to all ARPs or directly attached memory, and from the ARPs to the devices. Preferably, the ASW globally arbitrates the address bus, and all commands propagate at pre-defined clock cycles through the bus. Preferably, each device on the bus independently signals a response via a separate response link running directly to a global collector, which collects all responses and broadcasts a single system-wide response back to the devices.Type: GrantFiled: November 12, 1999Date of Patent: April 29, 2003Assignee: International Business Machines CorporationInventors: Robert Allen Drehmel, Kent Harold Haselhorst, Russell Dean Hoover, James Anthony Marcella, George Wayne Nation
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Patent number: 6526469Abstract: A processor-memory bus comprises a command portion for transmitting addresses and commands, having a unidirectional input portion for transmitting commands to a central repeater unit, and a unidirectional broadcast portion for broadcasting commands from the repeater. The input portion comprises a plurality of links running from different devices, wherein each link is less than the full width of the broadcast bus portion. A command is transmitted over the input portion in a plurality of bus cycles, and broadcast over the broadcast portion in a single bus cycle. Since multiple input links connect to the central command repeater, it is possible to keep the broadcast bus full notwithstanding the fact that multiple bus cycles are required to transmit an individual command on the input portion. Preferably, the links are arranged hierarchically, from processors to local repeaters, from local repeaters to the central repeater, and back again.Type: GrantFiled: November 12, 1999Date of Patent: February 25, 2003Assignee: International Business Machines CorporationInventors: Robert Allen Drehmel, Kent Harold Haselhorst, Russell Dean Hoover, James Anthony Marcella
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Patent number: 6523080Abstract: A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.Type: GrantFiled: January 27, 1998Date of Patent: February 18, 2003Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Robert Allen Drehmel, Lyle Edwin Grosbach, Kent Harold Haselhorst, David John Krolak, James Anthony Marcella, Peder James Paulson
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Patent number: 6513091Abstract: A method and apparatus for routing data between bus devices, where each bus device is connected to a centralized switch via a point-to-point bus connection. The plurality of point-to-point bus connections collectively form a system bus. After a command is issued on the system bus, each bus device responds to the issued command by transmitting an address status response to a response combining logic module. The response combining logic module identifies which of the bus devices responded with a positive acknowledgment to the issued command, then forwards a device identifier of the bus device responding with the positive acknowledgment to the switch. The switch uses the device identifier returned via the response combining logic to route the data transfer associated with the issued command.Type: GrantFiled: November 12, 1999Date of Patent: January 28, 2003Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Robert Allen Drehmel, Kent Harold Haselhorst, James Anthony Marcella
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Patent number: 6505306Abstract: An apparatus, program product and method initialize a redundant memory device by delaying the switchover of non-initialization fetch operations from a failed memory device to the redundant memory device until after initialization of the redundant memory device is complete. Consequently, during initialization, the non-initialization fetch operations are directed to the failed memory device, while non-initialization store operations are directed to the redundant device.Type: GrantFiled: September 15, 1999Date of Patent: January 7, 2003Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Robert Allen Drehmel, Kent Harold Haselhorst, James Anthony Marcella
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Patent number: RE44342Abstract: A processor-memory bus comprises a command portion for transmitting addresses and commands, having a unidirectional input portion for transmitting commands to a central repeater unit, and a unidirectional broadcast portion for broadcasting commands from the repeater. The input portion comprises a plurality of links running from different devices, wherein each link is less than the full width of the broadcast bus portion. A command is transmitted over the input portion in a plurality of bus cycles, and broadcast over the broadcast portion in a single bus cycle. Since multiple input links connect to the central command repeater, it is possible to keep the broadcast bus full notwithstanding the fact that multiple bus cycles are required to transmit an individual command on the input portion. Preferably, the links are arranged hierarchically, from processors to local repeaters, from local repeaters to the central repeater, and back again.Type: GrantFiled: August 15, 2005Date of Patent: July 2, 2013Assignee: International Business Machine CorporationInventors: Robert Allen Drehmel, Kent Harold Haselhorst, Russel Dean Hoover, James Anthony Marcella