Patents by Inventor James Apland

James Apland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6552410
    Abstract: A programmable circuit, such as a field programmable gate array, and a dedicated device, such as an ASIC type device, are coupled together with an antifuse based interface on a single integrated circuit. A configurable non-volatile memory that communicates with the dedicated device is also located on the integrated circuit. The platform for the programmable circuit is one half of an existing programmable circuit, which eliminates the need to engineer the programmable circuit. The programmable circuit includes a clock network that receives clock signals from clock terminals as well as from a clock network in the dedicated device. The interface between the dedicated device and programmable circuit includes a number of conductors with buffers with testing circuitry. The testing circuitry includes a PMOS test transistor and a NMOS test transistor which permits testing of the buffers without programming the antifuses coupled to the conductors.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: April 22, 2003
    Assignee: QuickLogic Corporation
    Inventors: David D. Eaton, Ket-Chong Yap, Kevin K. Yee, E. Thomas Hart, Andrew K. Chan, Neal A. Palmer, Michael W. Dini, James Apland, Panawalge S. N. Gunaratna
  • Patent number: 6130554
    Abstract: A programmable integrated circuit (see FIG. 13) includes a plurality of routing resources including collinearly extending routing wire segments and a test circuit for testing the integrity of the routing wire segments. The routing resource structures include a plurality of unprogrammed antifuses disposed between routing wire segments and a plurality of transistors disposed electrically in parallel with a corresponding respective one of the antifuses. The test circuit has a common node that may be coupled to a selected one of the routing resource structures for testing. In test mode, the test circuit detects whether a current flows through the selected routing resource structure and in response provides either a digital low value or a digital high value on an output node.
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: October 10, 2000
    Assignee: QuickLogic Corporation
    Inventors: Paige A. Kolze, Andrew K. Chan, James A. Apland
  • Patent number: 6084428
    Abstract: A field programmable gate array has columns of logic modules. A programming conductor used to conduct programming current to program antifuses of the field programmable gate array extends between two adjacent columns of logic modules. First wire segments extend from the programming conductor and toward the logic modules of a first of the two adjacent columns. Second wire segments extend the opposite direction from the programming conductor and toward logic modules of the second of the two adjacent columns. Programming current used to program antifuses disposed along the first wire segments as well as antifuses disposed along the second wire segments can be supplied from the same programming conductor that extends between the two columns of logic modules. The logic modules of the first column are mirrored versions of the logic modules of the second column.
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: July 4, 2000
    Assignee: QuickLogic Corporation
    Inventors: Paige A. Kolze, James A. Apland