Abstract: A circuit for tuning a transconductance amplifier includes a first transconductance amplifier outputting a first current from its output, a second transconductance amplifier outputting a second current from an output that is coupled to the output of the first transconductance amplifier, and a feedback loop. The feedback loop provides a control signal that varies with a difference between the first current and the second current and is used to adjust the transconductance of the second transconductance amplifier.

Abstract: An improved complementary logic driven level shifter which typically improves switching speed over the prior art diode-type circuit, and allows for symmetrical delays for both high-to-low and low-to-high transitions, thus reducing settling times. The complementary CMOS and not-CMOS inputs to the level shifter are applied to the gates of a pair of P-channel FETs and also to the gates of a pair of N-channel FETs. The sources of the P-channel FETs are coupled to a current source. The drain of each P-channel FET is coupled to the drain of the N-channel FET to which its gate is coupled, and also to the anode of a diode. The cathodes of the two diodes, and the sources of the N-channel FETs are coupled together to the anode of a grounded cathode diode. The output SELECT is the common connection point of the drains of the FETs whose gates are coupled to not-CMOS, and the complementary not-SELECT output is the drains of the FETs whose gates are coupled to CMOS.