Abstract: A system to mitigate errors in GPS corrections and ephemeris uncertainty data broadcast to a vehicle is presented. The system includes reference receivers in a first ground subsystem and a processor. The processor: receives, from reference receivers in a wide area network of reference receivers, satellite measurement data for a first plurality of satellites and receives, from the reference receivers in the first ground subsystem, satellite measurement data and ephemeris data from a second plurality of satellites; evaluate the satellite measurement data to determine if the GPS corrections are degraded by a current ionosphere disturbance activity; determine a current quality metric of the ionosphere; adjust a Vertical Ionosphere Gradient standard deviation sigma-vig; evaluate the ephemeris data to determine if the GPS corrections provided to the vehicle are degraded by ephemeris errors; and establish ephemeris uncertainty to protect integrity based on the evaluation of the ephemeris data.

Abstract: A method of using space based augmentation system (SBAS) ephemeris data in conjunction with a ground based augmentation systems (GBAS) station is provided. The method includes integrating a space based augmentation system (SBAS) receiver in the GBAS station; receiving an industry-standard message type via the SBAS receiver at the GBAS station; consuming, at the GBAS station, the SBAS ephemeris data from the industry-standard message type associated with satellites in view of the GBAS station. The industry-standard message type includes SBAS ephemeris data associated with satellites in a global navigation satellite system (GNSS). The method further includes, based on the consuming, improving error bounds to GBAS broadcast ephemeris decorellation parameters broadcast from the GBAS station and reducing time to reintroduce a satellite in the GNSS.

Abstract: A Ground-Based Augmentation System (GBAS) includes a plurality of Global Navigation Satellite System (GNSS) reference receivers configured to receive and process GNSS satellite measurements.

Abstract: Systems and methods for using multi frequency satellite measurements to mitigate spatial decorrelation errors caused by ionosphere delays are provided. In one embodiment, a GBAS comprises: a plurality of GNSS reference receivers that receive signals from GNSS satellites; at least one processing module; at least one aircraft communication device; wherein the processing module determines a TEC along a line of sight of a first observable multi-frequency GNSS satellite to determine a current quality metric of the ionosphere; determines at least one overbounded Vertical Ionosphere Gradient standard deviation sigma-vig (?vig) when the current quality metric of the ionosphere meets a threshold; defines one or more valid iono regions at a given finite period in time where at least one ?vig is applicable; and causes the communication device to communicate to an aircraft the ?vig and a list of GNSS single and multi-frequency satellites having pierce points in the valid iono regions.

Abstract: GBAS includes reference receivers, processing module, and communication device. Processing module checks GNSS satellite measurements to determine proximity of GNSS satellite measurement's IPP to IGPs derived from SBAS geostationary satellites. Processing module determines that GNSS satellite measurement is safe for mitigation using overbounded Vertical Ionosphere Gradient standard deviation sigma-vig (?vig) when IGPs possess acceptable GIVE values. Processing module determines whether number of GNSS satellite measurements determined safe for mitigation using ?vig are able to produce VPL that meets VAL required for precision approach.

Abstract: A ground-based system to reduce the effect of interference, comprising a plurality of reference receivers, wherein the reference receivers are spaced a distance apart such that a single source of interference is unable to substantially interfere with a subset of the plurality of reference receivers, wherein the subset of the plurality of reference receivers includes at least two reference receivers; and a processing module communicatively coupled to the plurality of reference receivers and configured to receive data from each of the plurality of reference receivers, wherein the processing module is further configured to perform differential calculations on the data to calculate measurement corrections and estimated errors.

Abstract: Systems and methods for characterizing regions of turbulence are provided. In one implementation, a method includes: measuring turbulence with an inertial reference unit on an aircraft to acquire a turbulence measurement; recording a position of the aircraft associated with the turbulence measurement and the turbulence measurement on at least one memory device; processing the turbulence measurement on a processing unit to determine a turbulence intensity setting; determining a turbulence region for the recorded position; associating the turbulence region with the turbulence intensity setting; and transmitting the turbulence intensity setting and the associated turbulence region.

Abstract: Systems and methods for characterizing regions of turbulence are provided. In one implementation, a method includes: measuring turbulence with an inertial reference unit on an aircraft to acquire a turbulence measurement; recording a position of the aircraft associated with the turbulence measurement and the turbulence measurement on at least one memory device; processing the turbulence measurement on a processing unit to determine a turbulence intensity setting; determining a turbulence region for the recorded position; associating the turbulence region with the turbulence intensity setting; and transmitting the turbulence intensity setting and the associated turbulence region.

Abstract: A disk array system comprises a plurality of controllers, each of which preferably implements a host side of an ATA interface protocol within automated circuitry to control a respective ATA disk drive. Each controller includes a command buffer for storing disk drive commands to be executed by a respective ATA drive, and includes a circuit that prefetches such commands so that a next disk drive command will be available within the command buffer when the disk drive finishes executing a current disk drive command. A delay that commonly occurs when an ATA disk drive retrieves a next disk drive command is thereby reduced or avoided. The disk drive commands are preferably dispatched to the controllers by a microcontroller over a control bus that is separate from a bus used for input/output data transfers.

Abstract: A disk array system comprises a plurality of automated controllers, each of which implements a host side of a standard ATA interface protocol within automated circuitry to control a respective disk drive. Each automated controller preferably includes a command buffer for storing disk drive commands to be executed by a respective ATA drive, and a data buffer that stores I/O data being transferred to or from the ATA disk drive. In a preferred embodiment, the automated controllers are connected by a control bus to a microcontroller that dispatches disk drive commands to the automated controllers in response to I/O requests from a host computer, and are also connected by a second bus to an automated processor. The automated processor transfers I/O data between the automated controllers/ATA disk drives and a host computer, and tracks the completion statuses of pending I/O requests.

Abstract: A disk array system comprises a plurality of automated controllers, each of which implements a host side of a standard ATA interface protocol within automated circuitry to control a respective disk drive. Each automated controller preferably includes a command buffer for storing disk drive commands to be executed by a respective ATA drive, and a data buffer that stores I/O data being transferred to or from the ATA disk drive. In a preferred embodiment, the automated controllers are connected by a control bus to a microcontroller that dispatches disk drive commands to the automated controllers in response to I/O requests from a host computer, and are also connected by a second bus to an automated processor. The automated processor transfers I/O data between the automated controllers/ATA disk drives and a host computer, and tracks the completion statuses of pending I/O requests.

Abstract: A high performance RAID system for a PC comprises a controller card which controls an array of ATA disk drives. The controller card includes an array of automated disk drive controllers, each of which controls one respective disk drive. The disk drive controllers are connected to a microcontroller by a control bus and are connected to an automated coprocessor by a packet-switched bus. The coprocessor accesses system memory and a local buffer. In operation, the disk drive controllers respond to controller commands from the microcontroller by accessing their respective disk drives, and by sending packets to the coprocessor over the packet-switched bus. The packets carry I/O data (in both directions, with the coprocessor filling-in packet payloads on I/O writes), and carry transfer commands and target addresses that are used by the coprocessor to access the buffer and system memory.

Abstract: A high-performance RAID system for a PC comprises a controller card which controls an array of ATA disk drives. The controller card includes an array of automated disk drive controllers, each of which controls one respective disk drive. The disk drive controllers are connected to a microcontroller by a control bus and are connected to an automated coprocessor by a packet-switched bus. The coprocessor accesses system memory and a local buffer. In operation, the disk drive controllers respond to controller commands from the microcontroller by accessing their respective disk drives, and by sending packets to the coprocessor over the packet-switched bus. The packets carry I/O data (in both directions, with the coprocessor filling-in packet payloads on I/O writes), and carry transfer commands and target addresses that are used by the coprocessor to access the buffer and system memory.

Abstract: A high-performance RAID system for a PC comprises a controller card which controls an array of ATA disk drives. The controller card includes an array of automated disk drive controllers, each of which controls one respective disk drive. The disk drive controllers are connected to a microcontroller by a control bus and are connected to an automated coprocessor by a packet-switched bus. The coprocessor accesses system memory and a local buffer. In operation, the disk drive controllers respond to controller commands from the microcontroller by accessing their respective disk drives, and by sending packets to the coprocessor over the packet-switched bus. The packets carry I/O data (in both directions, with the coprocessor filling-in packet payloads on I/O writes), and carry transfer commands and target addresses that are used by the coprocessor to access the buffer and system memory.

Abstract: A high-performance RAID system for a PC comprises a controller card which controls an array of ATA disk drives. The controller card includes an array of automated disk drive controllers, each of which controls one respective disk drive. The disk drive controllers are connected to a microcontroller by a control bus and are connected to an automated coprocessor by a packet-switched bus. The coprocessor accesses system memory and a local buffer. In operation, the disk drive controllers respond to controller commands from the microcontroller by accessing their respective disk drives, and by sending packets to the coprocessor over the packet-switched bus. The packets carry I/O data (in both directions, with the coprocessor filling-in packet payloads on I/O writes), and carry transfer commands and target addresses that are used by the coprocessor to access the buffer and system memory.

Abstract: A high-performance RAID system for a PC comprises a controller card which controls an array of ATA disk drives. The controller card includes an array of automated disk drive controllers, each of which controls one respective disk drive. The disk drive controllers are connected to a microcontroller by a control bus and are connected to an automated coprocessor by a packet-switched bus. The coprocessor accesses system memory and a local buffer. In operation, the disk drive controllers respond to controller commands from the microcontroller by accessing their respective disk drives, and by sending packets to the coprocessor over the packet-switched bus. The packets carry I/O data (in both directions, with the coprocessor filling-in packet payloads on I/O writes), and carry transfer commands and target addresses that are used by the coprocessor to access the buffer and system memory.