Abstract: The present disclosure generally relates to displaying information related to a physical activity. In some embodiments, methods and user interfaces for managing the display of information related to a physical activity are described.

Abstract: An apparatus for adjusting bandwidth for a receiver includes: (a) a receiver clock operating according to receiver clock parameters related to received signals for sampling received signals; (b) a local clock; (c) a tracker receiving an indicator related to the receiver clock parameter and generating a tracking parameter for comparing the receiver clock parameter and periodicity of the local clock; (d) a counter for counting events associated with the tracking parameter and generating an event count relating to the received signals; (e) a decision unit for reckoning the event count and generate a decision parameter relating to the reckoning; and (f) output logic coupled with the decision unit, the tracker and the receiver clock for evaluating the decision parameter and the tracking parameter by a logical routine for determining a need for changing operation of the receiver clock and for generating a change signal when the need exists.

Abstract: An apparatus and method of synthesizing an output clock signal from a source clock signal. The clock synthesizer includes a phase generator, a phase selector, a phase interpolator, and control circuitry for controlling the phase selector/interpolator. The phase generator receives a high speed clock, and generates P phases of the source clock to define P phase sectors. The phase selector selects respective pairs of phases such that each pair bounds a respective phase sector. The phase interpolator introduces at least one phase of the source clock between each pair of phases to provide Q phases of the source clock within each sector. The phase interpolator uses the phases of the source clock to produce lagging (leading) phase shifts of 360/P(Q?1) degrees, thereby generating the output clock having a stepped up or stepped down frequency.

Abstract: An automatic bit-rate detection scheme (30) for use in SONET/SDH transceivers (12, 14) that uses only one clocking frequency (clk), is all digital, and requires less than 250 microseconds to detect a new data bit-rate. The present invention analyzes events that are guaranteed to be present in all SONET data streams. A1 and A2 framing bytes (22,24) occur at 125 microseconds intervals in all SONET signals. The bit transitions in the framing bytes represent the minimum transition intervals of the received data. The present invention examines this bit interval to determine the operating frequency of the received data. A set of combinational logic circuits (70, 80, 90) are used to detect specific data bit patterns which appear in the A1 and A2 SONET framing bytes, such as “010” and “101”. The combinational circuit looks for specific patterns of data bits occurring at a specific communication rate.

Abstract: A loss of lock condition of a clock signal (25) recovered from a received data stream can be detected by examining conventionally available information (25, 26) indicative of a rate of change of an interpolation ratio according to which first and second phases of a local reference clock signal are combined to form the recovered clock signal.

Abstract: An apparatus for adjusting bandwidth for a receiver includes: (a) a receiver clock operating according to receiver clock parameters related to received signals for sampling received signals; (b) a local clock; (c) a tracker receiving an indicator related to the receiver clock parameter and generating a tracking parameter for comparing the receiver clock parameter and periodicity of the local clock; (d) a counter for counting events associated with the tracking parameter and generating an event count relating to the received signals; (e) a decision unit for reckoning the event count and generate a decision parameter relating to the reckoning; and (f) output logic coupled with the decision unit, the tracker and the receiver clock for evaluating the decision parameter and the tracking parameter by a logical routine for determining a need for changing operation of the receiver clock and for generating a change signal when the need exists.

Abstract: A loss of lock condition of a clock signal (25) recovered from a received data stream can be detected by examining conventionally available information (25, 26) indicative of a rate of change of an interpolation ratio according to which first and second phases of a local reference clock signal are combined to form the recovered clock signal.

Abstract: A fault tolerant register employing triple redundant storage of data and continuous voting to protect the data from Single Event Upset, or SEU. The fault tolerant register includes a single master multiplexer, three slave multiplexers connected in parallel to the output of the master multiplexer and three voting circuits positioned in feedback paths of the slave multiplexers. The slave multiplexers provide triple redundant storage for the data and the voting circuits correct any data that might become disrupted. The fault tolerant register of the present invention provides greatly improved SEU tolerance without a large increase in circuit area or without resorting to error correction and its attendant scrubbing process.

Abstract: An adjunct switch circuit is provided for detecting power to ground leaks in a portion of a chip circuit and for disabling such circuit portion in the event of a leak. The switch circuit of the invention is particularly useful for Wafer Scale Integration, and is conveniently employed in the testing of chip circuits following manufacturing.In a preferred embodiment, the switch circuit includes a power supply, including a voltage source and a ground, a reset line for receiving a reset pulse, a first switch, connected in series with one of the power supply lines to the circuit portion ground and inversely responsive to both the reset pulse and the state of the circuit portion ground following termination of the reset pulse, and a second switch, connected between ground and the circuit portion ground and directly responsive to the reset pulse to leak current from the circuit portion ground to ground when turned on by the reset pulse.