Patents by Inventor James B. Cser

James B. Cser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for changing the weight of a synaptic element
    Patent number: 6023422
    Abstract: An analog storage array according to the present invention is disposed on a semiconductor substrate. The array is arranged as a plurality of rows and a plurality of columns and includes a plurality of N-channel MOS transistors disposed in the rows and columns in a p-well in the semiconductor substrate. Each of the MOS transistors includes a source, a drain, and a floating gate forming a tunneling junction with a tunneling electrode. An input line is associated with each of the rows in the array. Each input line is connected to the source of each of the N-channel MOS transistors disposed in the row with which the input line is associated. A bias line is associated with each of the rows in the array. Each bias line is capacitively coupled to the floating gate of each of the N-channel MOS transistors disposed in the row with which the bias line is associated. A tunnel line is associated with each of the columns in the array.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: February 8, 2000
    Assignee: Synaptics, Inc.
    Inventors: Timothy P. Allen, James B. Cser
  • One-transistor adaptable analog storage element and array
    Patent number: 5864242
    Abstract: An analog storage array according to the present invention is disposed on a semiconductor substrate. The array is arranged as a plurality of rows and a plurality of columns and includes a plurality of N-channel MOS transistors disposed in the rows and columns in a p-well in the semiconductor substrate. Each of the MOS transistors includes a source, a drain, and a floating gate forming a tunneling junction with a tunneling electrode. An input line is associated with each of the rows in the array. Each input line is connected to the source of each of the N-channel MOS transistors disposed in the row with which the input line is associated. A bias line is associated with each of the rows in the array. Each bias line is capacitively coupled to the floating gate of each of the N-channel MOS transistors disposed in the row with which the bias line is associated. A tunnel line is associated with each of the columns in the array.
    Type: Grant
    Filed: December 11, 1995
    Date of Patent: January 26, 1999
    Assignee: Synaptics Incorporated
    Inventors: Timothy P. Allen, James B. Cser
  • One-transistor adaptable analog storage element and array
    Patent number: 5336936
    Abstract: An analog storage array according to the present invention is disposed on a semiconductor substrate. The array is arranged as a plurality of rows and a plurality of columns and includes a plurality of N-channel MOS transistors disposed in the rows and columns in a p-well in the semiconductor substrate. Each of the MOS transistors includes a source, a drain, and a floating gate forming a tunneling junction with a tunneling electrode. An input line is associated with each of the rows in the array. Each input line is connected to the source of each of the N-channel MOS transistors disposed in the row with which the input line is associated. A bias line is associated with each of the rows in the array. Each bias line is capacitively coupled to the floating gate of each of the N-channel MOS transistors disposed in the row with which the bias line is associated. A tunnel line is associated with each of the columns in the array.
    Type: Grant
    Filed: May 6, 1992
    Date of Patent: August 9, 1994
    Assignee: Synaptics, Incorporated
    Inventors: Timothy P. Allen, James B. Cser