Abstract: A modular chip select control circuit (80) is scalable by having an address decode stage (90) with a first number of address decoders, a control stage (100) with a second number of control units, and a pin configuration stage (110) with a third number of pin configuration logic circuits. These three numbers, defining the number of memory regions, the access pipeline depth, and the number of chip select signals, respectively, are independent and may be changed between chip designs to accommodate different system needs. The control stage includes an early pipeline control circuit (186) which allows the control units (170, 180) to pipeline pending memory cycles, based on an accessed region's characteristics. The early pipeline control circuit (186) together with the control units (170, 180) enforce a set of pipelining rules to ensure data integrity and proper cycle termination, thus providing an efficient series of pipelined memory access cycles.

Abstract: A pin configuration logic circuit (120) has a pin function register (130) which defines a selected pin function, such as chip enable, write enable, and output enable, to be provided as a chip select signal. The logic circuit (120) allows an arbitrary pipeline length by causing the chip select signal to obey only the timing of the active cycle. For a two-deep access pipeline, the logic circuit (120) marks whether a first or a second cycle owns the pin. The pin configuration logic circuit (120) uses the timing associated with the selected pin function to provide the chip select signal during the first cycle if the attributes of the cycle, such as an access to a region programmed in the pin function register, are met. During the second cycle, the pin configuration logic circuit (120) further obeys the timing associated with the selected pin function if the attributes of that cycle are also met.

Abstract: An integrated circuit microprocessor has on-board programmable chip select logic. Each of several chip select outputs is individually programmable by means of one or more control register bit fields. For instance, each chip select is asserted for bus cycles within an address range whose starting address and block size are both programmable. In addition, each chip select can be programmed to be active on read cycles only, on write cycles only, or on both read and write cycles. Each chip select can be programmed to be active during interrupt acknowledge cycles only if the interrupt being acknowledged has the same priority level as has been programmed for that chip select. In addition, the timing of the assertion of each chip select is programmable to coincide with either the address strobe or data strobe of the bus cycle. The chip select logic is designed so that it is configured to come out of reset by producing an active chip select signal during the first bus cycle run by the processor following the reset.

Abstract: A data processing apparatus having a bus speed counter for determining the bus speed of a previous bus cycle. This previous bus speed information is then used to optimize bus utilization. This bus speed information is particularly useful for determining whether to run prefetch bus cycles during the execution of a conditional branch instruction. If previous bus cycles have been slow, prefetch procrastination can occurs until the branch condition resolves.

Abstract: A data processor having a microsequencer which reduces power consumption selectively activates instruction decode units and a microcode sequence control memory unit. The microsequencer has an instruction decode unit implemented with a plurality of PLAs and also has a microcoded ROM for providing the next microaddress. The instruction decode unit outputs a next microaddress, a next-PLA field, and a ROM-or-PLA control bit. The control bit functions to minimize power in the data processor. The next-PLA field is latched and used to select a single decode unit when the next instruction decode is needed to activate a predetermined decode unit. Early macroinstruction branching can be performed in the data processor thereby improving performance.

Abstract: A data processor having a microsequencer which reduces power consumption selectively activates instruction decode units and a microcode sequence control memory unit. The microsequencer has an instruction decode unit implemented with a plurality of PLAs and also has a microcoded ROM for providing the next microaddress. The instruction decode unit outputs a next microaddress, a next-PLA field, and a ROM-or-PLA control bit. The control bit functions to minimize power in the data processor. The next-PLA field is latched and used to select a single decode unit when the next instruction decode is needed to activate a predetermined decode unit. Early macroinstruction branching can be performed in the data processor thereby improving performance.

Abstract: A data processing system having a direct memory access controller (DMAC) which can be interrupted with a prioritized signal to vary bus mastership of a communication bus in the system. A prioritized interrupt signal is sent to a CPU when the DMAC has bus mastership. The CPU only informs the DMAC of the highest priority cumulative interrupt priority. With the use of a mask value, the interrupt may be selectively screened by the DMAC so that selective interrupts may remove bus mastership from the DMAC.