Abstract: This invention discloses a content addressable memory (CAM) cell having a SRAM portion and a tag-compare portion. The tag-compare portion includes six NMOS transistors, designated as M7 to M12, wherein a source of M7 is connected to a drain of M8, a drain of M7 is connected to a match line ML, a source of M8 is grounded; a body of M7 and a body of M8 are tied together at a source of M11, a gate of M7 and a gate of M11 are tied together to a first node n1, a gate of M8 and a drain of M11 are connected to a first digit line DLB; and a source of M9 is connected to a drain of M10, a drain of M9 is connected to said match line ML, a source of M10 is grounded; a body of M9 and a body of M10 are tied together at a source of M12, a gate of M9 and a gate of M12 are tied together to a second node n2, a gate of M10 and a drain of M12 are connected to a second digit line DL. The first and second nodes n1 and n2 are internal storage nodes of the SRAM portion.

Abstract: This invention reports a two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability. With an unique structure by connecting the source terminal of an NMOS device in the SRAM cell to the write word line, this SRAM cell can be used to provide SBLSRWA capability for 1V two-port VLSI SRAM as verified by SPICE results.

Abstract: This invention discloses a novel low-voltage two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access capability using partially-depleted SOI CMOS dynamic-threshold technique. With an innovative approach by connecting the body terminal of an NMOS device in the latch and the write access pass transistor to the write word line, this 6T memory cell can be used to provide SBLSRWA capability for 0.7 V two-port SOI CMOS VLSI SRAM as verified by MEDICI results.

Abstract: This invention presents an all-N-logic true-single-phase CMOS dynamic logic circuit for high speed operation with a low supply voltage, in which a bootstrapped circuit containing a bootstrap capacitor, an inverter and a PMOS transistor is incorporated to a conventional non-inverting N1-block.

Abstract: This invention discloses a 1.5 V bootstrapped pass-transistor-based Manchester-carry-chain circuit suitable for CMOS VLSI using a low supply voltage, in which a bootstrapper circuit is incorporated to enhance the speed performance of the conventional Manchester-carry-chain circuit, which is composed. The bootstrapper circuit contains two P-type metal-oxide-semiconductor (PMOS) transistors, one N-type metal-oxide-semiconductor (NMOS) transistor; a capacitor device, and an inverter. The bootstrapper circuit provides an output having a voltage overshoot, as a carry propagation signal, to the gate of a pass transistor of the Manchester-carry-chain circuit.

Abstract: A 1.5V full-swing bootstrapped CMOS large capacitive-load driver circuit using two bootstrap capacitors to enhance the switching speed for low-voltage deep-submicron CMOS VLSI. For a supply voltage of 1.5V, the full-swing bootstrapped CMOS driver circuit shows a 2.2 times improvement in switching speed in driving a capacitive load of 10 pF as compared to the conventional CMOS driver circuit. Even for a supply voltage of 1V, this full-swing bootstrapped CMOS large capacitive-load driver circuit is still advantageous.