Abstract: A wireless sensor assembly incudes a housing, a wireless power source, a wireless communication component, and firmware. The housing defines a first aperture for receiving an external sensor and a second aperture defining a communication port configured to receive a wire harness. The wireless communications component and the firmware are powered by the wireless power source. The wireless communications component is configured to be in electrical communication with the external sensor and transmit data from the external sensor to an external device. The firmware is configured to manage a rate of data transmittal from the wireless communications component to the external device. The wireless power source, the wireless communications component, and the firmware are mounted within the same housing. The data from the external sensor is transmitted from the external sensor wirelessly through the wireless communications component or through the wire harness to the external device for processing.

Abstract: A wireless sensor assembly includes a housing defining a first aperture for receiving an external sensor, and a second aperture defining a communication port, a wireless power source mounted within the housing, and electronics mounted to the housing and configured to receive power from the wireless power source and to be in electrical communication with the external sensor. The electronics include a wireless communications component, and firmware configured to manage a rate of data transmittal from the wireless communications component to an external device. The communication port is configured to receive a wire harness connected to the external sensor.

Abstract: A wireless sensor assembly includes a housing defining a first aperture for receiving an external sensor, and a second aperture defining a communication port, a wireless power source mounted within the housing, and electronics mounted to the housing and configured to receive power from the wireless power source and to be in electrical communication with the external sensor. The electronics include a wireless communications component, and firmware configured to manage a rate of data transmittal from the wireless communications component to an external device. The communication port is configured to receive a wire harness connected to the external sensor.

Abstract: Transparent ink-jet recording films, compositions, and methods are disclosed. These films can exhibit high maximum optical densities, rapid ink drying, low curl, excellent adhesion between the coating layers and the substrate, and negligible ink transfer between stacked ink-jet recording films after imaging. Such films are useful in medical imaging applications.

Abstract: A comparator circuit (300) has a first field effect transistor (FET) (307) with a supply voltage (301) connection and a diode connected FET (303) connected in series to form the first circuit leg of the comparator (300). A second diode connected FET (309) and a second FET (305) in series form the second circuit leg. The first FET (307) and said second FET (305) are approximately equal sized FETs. Another embodiment is an integrated circuit (401) with two n-channel FETs. A first diode connected FET (303) is connected to the first n-channel FET (307) in series to form the first circuit leg of a comparator (300) and a second diode connected FET (309) is connected to a second n-channel FET (305) in series to form the second circuit leg of the comparator. The two n-channel FETs that form the differential pair are approximately equal in size. The trip point is high with respect to the supply voltage.

Abstract: A comparator circuit (300) has a first field effect transistor (FET) (307) with a supply voltage (301) connection and a diode connected FET (303) connected in series to form the first circuit leg of the comparator (300). A second diode connected FET (309) and a second FET (305) in series form the second circuit leg. The first FET (307) and said second FET (305) are approximately equal sized FETs. Another embodiment is an integrated circuit (401) with two n-channel FETs. A first diode connected FET (303) is connected to the first n-channel FET (307) in series to form the first circuit leg of a comparator (300) and a second diode connected FET (309) is connected to a second n-channel FET (305) in series to form the second circuit leg of the comparator. The two n-channel FETs that form the differential pair are approximately equal in size. The trip point is high with respect to the supply voltage.

Abstract: A Finite Impulse Response (FIR) filter circuit (60) includes delay elements (63, 64, 66), multipliers (71, 72, 73, 74), a summing device (78), and a digital integrator (69) at the output of the FIR filter circuit (60). A method for processing data using the FIR filter circuit (60) includes differentially encoding data prior to storing or processing of the data. The method provides a technique for compressing data since less memory is needed to store derivative data. The method further includes integrating the derivative data using the digital integrator (69) to decompress the derivative data.

Abstract: A tuning circuit (202) uses a precision current reference (Iref) along with an analog-to-digital converter (218) to produce a digital output (228) to represent variations of internal resistance values. The precision current reference (Iref) is fed to an internal tuning resistor (R210) in order to provide an analog voltage signal to the analog-to-digital converter (218). The analog voltage signal changes in accordance with the variations in the tuning resistor value over process and temperature. The digital output (228) controls programmable capacitor arrays (C220, C222) which are included in the tuning circuit (202) as well as in an active RC filter (208) whose bandwidth is controlled by the programmable capacitor arrays (C220, C222) and internal resistors (R212, R214, R216).

Abstract: A transconductance scaling circuit (500) includes an operational transconductance amplifier (504) having a tunable voltage, V.sub.tune2. A feedback loop controls the tunable voltage, V.sub.tune2, in response to the digital programming of the transconductance amplifier (504) and provides the tunable voltage as a current scaling output.

Abstract: A DC translation circuit (200) provides maximum dynamic range in DC level shifting that is temperature and process invariant. The DC translation circuit (200) includes a bandgap reference (202) and current mirror circuit (204) for providing a reference current, Iref. An op-amp circuit (210) receives an AC signal centered about a first DC level, and translates the first DC level into a second DC level using the reference current, a current mirror circuit (208), op-amp circuit (210) and resistor (R2).

Abstract: A continuous time common mode feedback amplifier CTCMFB (300) is suitable for applications requiring fully differential amplifiers in low voltage supply requirements. Two mirror image, low gain CMOS amplifiers (MP0/MP2 and MP3/MP4) in the CTCMFB (300) define and stabilize the common mode output voltage, Vcm, of the main differential amplifier (102). The transient response of the common mode amplifier (300) can be adjusted independently of the transient response of the main differential amplifier (102), allowing fast transient response to the main differential amplifier.