Abstract: Approximations of reciprocal square roots are provided in IEEE floating point binary format by obtaining an index from an input value, accessing a pair of table values and performing a limited number of simple and rapidly performed manipulations. The maximum relative error in the approximation thus provided is less than 0.75/2(2k+1) as compared with a maximum relative error of 1/2k+2 of known methods, where 2k is the number of table entries.

Abstract: Approximations of reciprocal square roots are provided in IEEE floating point binary format by obtaining an index from an input value, accessing a pair of table values and performing a limited number of simple and rapidly performed manipulations. The maximum relative error in the approximation thus provided is less than 0.75/2(2k+1) as compared with a maximum relative error of 1/2k+2 of known methods, where 2k is the number of table entries.

Abstract: A digital watermarking method encodes different pairs of watermarks into each of a plurality of images offered for use by a vendor. The watermarks in each pair are derived from two separate collections of watermarks and sufficiently different so as to prevent false positives. Because each pair of watermarks is assigned to a different customer relative to a particular image, unauthorized use of a digital image sold to a customer may be determined by locating the associated pair of watermarks assigned to the customer in the image. Collusion detection is also realized by forming each pair of masks from sub-collections of masks which are detectable in an image formed by combining the same images sold to one or more customers.

Abstract: A vector having a plurality of elements is stored in an input storage area, wherein the vector elements are stored in a first pattern. Thereafter, the elements are transferred, in a first order, from the input storage area into a vector register interface unit. From the vector register interface unit, the elements are transferred to an output storage area and stored in addressable locations in one of a plurality of preselected patterns. The input storage area may be implemented with cache memory or a register array. The output storage area may be implemented with a cache memory or a register array. The first pattern in the input storage area may include alternating real and imaginary elements. The plurality of preselected patterns may include a reversed order pattern, or a separation of real and imaginary elements into two vector registers.

Abstract: In a vector processing system for processing vector calculations utilizing a portion of a vector comprising a plurality of elements, means for receiving a vector and a vector processing command are provided. The vector processing system also includes means for receiving and storing a start-element value and an end-element value. An arithmetic logic unit is coupled to the means for receiving the vector, the means for receiving the vector processing command, and the means for receiving the start-element and end-element values. The arithmetic logic unit also includes means for executing the vector processing command utilizing only one or more of the elements in the vector, which are selected by the start-element value and the end-element value.