Patents by Inventor James B. Wieser

James B. Wieser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8591427
    Abstract: A system includes at least one first magnetic field sensor configured to measure first and second magnetic fields. The system also includes at least one second magnetic field sensor configured to measure the second magnetic field substantially without measuring the first magnetic field. The system further includes processing circuitry configured to perform signal cancellation to generate measurements of the first magnetic field and to generate an output based on the measurements of the first magnetic field. The sensors could represent magneto-electric sensors. The magneto-electric sensors could be configured to up-convert electrical signals associated with the first and/or second magnetic fields to a higher frequency. The processing circuitry could be configured to identify one or more problems associated with a patient's heart.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: November 26, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Lawrence H. Zuckerman, Michael X. Maida, Dennis M. Monticelli, James B. Wieser, Jamal Ramdani, Paul Mawson, Moulay Mohamed Ibourk
  • Patent number: 8581579
    Abstract: A method includes generating an electrical signal representing a magnetic field using a magnetic field sensor having alternating layers of magneto-strictive material and piezo-electric material. The method also includes performing up-conversion or down-conversion so that the electrical signal representing the magnetic field has a higher or lower frequency than a frequency of the magnetic field. The up-conversion or down-conversion is performed before the magnetic field is converted into the electrical signal. The up-conversion or down-conversion could be performed by repeatedly sensitizing and desensitizing the magnetic field sensor. This could be done using a permanent magnet and an electromagnet, an electromagnet without a permanent magnet, or a movable permanent magnet. The up-conversion or down-conversion could also be performed by chopping the magnetic field.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: November 12, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Lawrence H. Zuckerman, Michael X. Maida, Dennis M. Monticelli, James B. Wieser, Jamal Ramdani
  • Patent number: 8447000
    Abstract: A receiver that easily receives signals from transmission channels having long cable lengths is presented. The receiver includes an analog pre-filter that removes distortions and intersymbol interference from a predetermined transmission channel. The analog pre-filter is coupled with a digital receiver that provides digital equalization. The combination of analog equalization with digital equalization allows for simplified digital equalization while retaining the versatility of digital signal processing.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: May 21, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Tulsi Manickam, Peter J. Sallaway, Sreen A. Raghavan, Abhijit M. Phanse, James B. Wieser
  • Publication number: 20120183025
    Abstract: A receiver that easily receives signals from transmission channels having long cable lengths is presented. The receiver includes an analog pre-filter that removes distortions and intersymbol interference from a predetermined transmission channel. The analog pre-filter is coupled with a digital receiver that provides digital equalization. The combination of analog equalization with digital equalization allows for simplified digital equalization while retaining the versatility of digital signal processing.
    Type: Application
    Filed: January 12, 2009
    Publication date: July 19, 2012
    Inventors: Tulsi Manickam, Peter J. Sallaway, Sreen A. Raghavan, Abhijit M. Phanse, James B. Wieser
  • Patent number: 8005135
    Abstract: An analog equalizer (613 and 614) adaptively equalizes an input analog signal affected with intersymbol interference (“ISI”), or an intermediate analog signal generated therefrom, to produce a filtered partially equalized analog signal with reduced ISI. An analog-to-digital converter (210) converts the filtered analog signal, or an intermediate analog signal generated therefrom, into an initial digital signal. A digital equalizer (212) adaptively equalizes the initial digital signal, or an intermediate digital signal generated therefrom, to produce an equalized digital signal as a stream of equalized digital values with further reduced ISI. An output decoder (605) decodes the equalized digital values, or intermediate digital values generated therefrom, into a stream of symbols.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: August 23, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Tulsi Manickam, Peter J. Sallaway, Sreen A. Raghavan, Abhijit M. Phanse, James B. Wieser
  • Publication number: 20110148403
    Abstract: A method includes generating an electrical signal representing a magnetic field using a magnetic field sensor having alternating layers of magneto-strictive material and piezo-electric material. The method also includes performing up-conversion or down-conversion so that the electrical signal representing the magnetic field has a higher or lower frequency than a frequency of the magnetic field. The up-conversion or down-conversion is performed before the magnetic field is converted into the electrical signal. The up-conversion or down-conversion could be performed by repeatedly sensitizing and desensitizing the magnetic field sensor. This could be done using a permanent magnet and an electromagnet, an electromagnet without a permanent magnet, or a movable permanent magnet. The up-conversion or down-conversion could also be performed by chopping the magnetic field.
    Type: Application
    Filed: November 9, 2010
    Publication date: June 23, 2011
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Lawrence H. Zuckerman, Michael X. Maida, Dennis M. Monticelli, James B. Wieser, Jamal Ramdani
  • Publication number: 20110152703
    Abstract: A system includes at least one first magnetic field sensor configured to measure first and second magnetic fields. The system also includes at least one second magnetic field sensor configured to measure the second magnetic field substantially without measuring the first magnetic field. The system further includes processing circuitry configured to perform signal cancellation to generate measurements of the first magnetic field and to generate an output based on the measurements of the first magnetic field. The sensors could represent magneto-electric sensors. The magneto-electric sensors could be configured to up-convert electrical signals associated with the first and/or second magnetic fields to a higher frequency. The processing circuitry could be configured to identify one or more problems associated with a patient's heart.
    Type: Application
    Filed: November 9, 2010
    Publication date: June 23, 2011
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Lawrence H. Zuckerman, Michael X. Maida, Dennis M. Monticelli, James B. Wieser, Jamal Ramdani, Paul Mawson, Moulay Mohamed Ibourk
  • Patent number: 7756228
    Abstract: Analog echo-cancelling circuitry (611 and 627) operates on an input analog signal that includes an echo of an output signal, or on an analog signal generated from the input signal, to produce an analog signal with reduced echo. An analog-to-digital converter (210) converts the echo-reduced analog signal, or an analog signal generated therefrom, into a digital signal. Digital echo-cancelling circuitry (615 and 621) operates on the digital signal, or on a digital signal generated therefrom, to produce a digital signal with further reduced echo. An output decoder (605) decodes the echo-reduced digital signal, or a digital signal generated therefrom, into a stream of symbols. The echo-filtering characteristics of both echo-cancelling circuitries are typically adaptively adjusted during generation of the symbol stream. The analog echo-filtering characteristics may be adapted in response to information provided by operating on the echo-reduced digital signal or on a digital signal generated therefrom.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: July 13, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Tulsi Manickam, Peter J. Sallaway, Sreen A. Raghavan, Abhijit M. Phanse, James B. Wieser
  • Patent number: 7728399
    Abstract: Apparatuses and methods directed to an integrated circuit package having an optical component are disclosed. The package may include an integrated circuit die having at least one light sensitive region disposed on a first surface thereof. By way of example, the die may be a laser diode that emits light through the light sensitive region, or a photodetector that receives and detects light through the light sensitive region. An optical concentrator may be positioned adjacent the first surface of the first die. The optical concentrator includes a lens portion positioned adjacent the light sensitive region and adapted to focus light.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: June 1, 2010
    Assignees: National Semiconductor Corporation, The Regents of the University of California
    Inventors: Randall L. Walberg, Luu T. Nguyen, Robert Dahlgren, James B. Wieser, Kenneth Pedrotti, Jacob A. Wysocki
  • Patent number: 7664172
    Abstract: A receiver system contains an analog pre-filter (207 or 619), an analog-to-digital converter (210), a digital equalizer (212), and a decoder (605) arranged sequentially for processing an input analog signal (yk). The pre-filter produces a filtered analog signal (Zs) with reduced intersymbol interference. The converter provides analog-to-digital signal conversion. Digital equalization circuitry in the equalizer operates according to a transfer frmnction c - 1 ? z + c 0 + ? M i = 1 ? c i ? z - i to produce an equalized digital signal (a'k) as a stream of equalized digital values. Coefficients c?1 and c0 are fixed. Each other coefficient ci is adaptively chosen. The decoder converts the equalized digital values, or intermediate values generated therefrom, into a stream of symbols.
    Type: Grant
    Filed: August 15, 2006
    Date of Patent: February 16, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Tulsi Manickam, Peter J. Sallaway, Sreen A. Raghavan, Abhijit M. Phanse, James B. Wieser
  • Publication number: 20100019339
    Abstract: Apparatuses and methods directed to an integrated circuit package having an optical component are disclosed. The package may include an integrated circuit die having at least one light sensitive region disposed on a first surface thereof. By way of example, the die may be a laser diode that emits light through the light sensitive region, or a photodetector that receives and detects light through the light sensitive region. An optical concentrator may be positioned adjacent the first surface of the first die. The optical concentrator includes a lens portion positioned adjacent the light sensitive region and adapted to focus light.
    Type: Application
    Filed: July 22, 2008
    Publication date: January 28, 2010
    Applicants: NATIONAL SEMICONDUCTOR CORPORATION, THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Randall L. WALBERG, Luu T. NGUYEN, Robert DAHLGREN, James B. WIESER, Kenneth PEDROTTI, Jacob A. WYSOCKI
  • Patent number: 7646807
    Abstract: An analog equalizer (613 and 614) adaptively equalizes an input analog signal affected with intersymbol interference (“ISI”), or an intermediate analog signal generated therefrom, to produce a filtered partially equalized analog signal with reduced ISI. An analog-to-digital converter (210) converts the filtered analog signal, or an intermediate analog signal generated therefrom, into an initial digital signal. A digital equalizer (212) adaptively equalizes the initial digital signal, or an intermediate digital signal generated therefrom, to produce an equalized digital signal as a stream of equalized digital values with further reduced ISI. An output decoder (605) decodes the equalized digital values, or intermediate digital values generated therefrom, into a stream of symbols.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: January 12, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Tulsi Manickam, Peter J. Sallaway, Sreen A. Raghavan, Abhijit M. Phanse, James B. Wieser
  • Patent number: 7454647
    Abstract: A skew measurement system and method wherein each of the signals among which the skew is to be determined is connected one at a time to a clock recovery loop. The locked state of the clock recovery loop is used as an indicator of the skew of the data signal relative to the internal clock of the clock recovery loop. By measuring the difference between the locked state of different signals, their relative skew can be measured.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: November 18, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Varadarajan Devnath, Vijaya Ceekala, James B. Wieser, Lawrence K. Whitcomb
  • Patent number: 7307458
    Abstract: A serial communication interface driver is provided wherein current steering switches are also used to provide termination impedances. The output voltage can be produced by a voltage-dividing current path between two regulated voltages, which provides improved efficiency.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: December 11, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Alan E. Segervall, Vijaya Ceekala, Varadarajan Devnath, James B. Wieser
  • Patent number: 7254198
    Abstract: A receiver system suitable for a local area network contains an analog pre-filter (207 or 619), an analog-to-digital converter (210), a digital equalizer (212), and a decoder (605). A symbol-information-carrying input analog signal (yk), or a first intermediate analog signal generated from the input analog signal, is filtered by filtering circuitry in the pre-filter to produce a filtered analog signal (Zs) with reduced intersymbol interference. The filtering circuitry operates according to a transfer function such as (b1s+1)/(a2s2+a1s+1) or (1?Vc)+VcPF(s) where Vc is adaptively varied. The analog-to-digital converter provides analog-to-digital signal conversion. The equalizer provides digital signal equalization to produce an equalized digital signal (a?k) as a stream of equalized digital values. The decoder converts the equalized digital values, or intermediate digital values generated from the equalized digital values, into a stream of symbols.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: August 7, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Tulsi Manickam, Peter J. Sallaway, Sreen A. Raghavan, Abhijit M. Phanse, James B. Wieser
  • Patent number: 7208981
    Abstract: A circuit and method are provided for performing built-in test of output signal magnitudes of integrated differential signal generator circuitry. In accordance with one embodiment, first upper and lower reference voltages and second upper and lower reference voltages are received via a plurality of reference electrodes, wherein: a difference between the first and upper and lower reference voltages comprises a first difference magnitude; a difference between the second upper and lower reference voltages comprises a second difference magnitude; and the first difference magnitude is greater than the second difference magnitude. Test signal generator circuitry provides a plurality of binary signals with respective successions of opposing signal states.
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: April 24, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Ramsin M. Ziazadeh, Vijaya Ceekala, Matthew James Webb, James B. Wieser
  • Patent number: 7065133
    Abstract: There is disclosed a transceiver for use in a high speed Ethernet local area network (LAN). The transceiver comprises: 1) front-end analog signal processing circuitry comprising: a) a line driver for transmitting an outgoing analog signal to an external cable; b) a DC offset correction circuit for reducing a DC component in an incoming analog signal; c) an echo canceller; d) an automatic gain control (AGC) circuit; and e) an adaptive analog equalization filter. The transceiver also comprises: 2) an analog-to-digital converter (ADC) for converting the analog filter incoming signal to a first incoming digital signal; and 3) digital signal processing circuitry comprising: a) a digital finite impulse response (FIR) filter; b) a digital echo cancellation circuit to produce a reduced-echo incoming digital signal; c) a digital automatic gain control (AGC) circuit; and d) a digital base line wander circuit.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: June 20, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Abhijit M. Phanse, Peter J. Sallaway, James B. Wieser
  • Patent number: 6930537
    Abstract: A band-gap reference circuit with averaged current mirror offsets is provided that includes a differential amplifier circuit, a low current transistor circuit, a high current transistor circuit, and a configuration circuit. The differential amplifier circuit includes a first input node operable to receive a first input signal, a second input node operable to receive a second input signal, and an output node operable to generate an output signal based on the input signal difference. The low current transistor circuit is coupled to the differential amplifier circuit and is operable to receive the output signal and to generate the first input signal based on the output signal. The high current transistor circuit is coupled to the differential amplifier circuit and is operable to receive the output signal and to generate the second input signal based on the output signal. The configuration circuit is coupled to the low current transistor circuit and to the high current transistor circuit.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: August 16, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Vijaya G. Ceekala, James B. Wieser, Devnath Varadarajan, Laurence D. Lewicki, Jitendra Mohan
  • Patent number: 6795494
    Abstract: There is disclosed a transceiver for use in a high speed Ethernet local area network (LAN). The transceiver comprises: 1) front-end analog signal processing circuitry comprising: a) a line driver for transmitting an outgoing analog signal to an external cable; b) a DC offset correction circuit for reducing a DC component in an incoming analog signal; c) an echo canceller; d) an automatic gain control (AGC) circuit; and e) an adaptive analog equalization filter. The transceiver also comprises: 2) an analog-to-digital converter (ADC) for converting the analog filter incoming signal to a first incoming digital signal; and 3) digital signal processing circuitry comprising: a) a digital finite impulse response (FIR) filter; b) a digital echo cancellation circuit to produce a reduced-echo incoming digital signal; c) a digital automatic gain control (AGC) circuit; and d) a digital base line wander circuit.
    Type: Grant
    Filed: May 12, 2000
    Date of Patent: September 21, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Abhijit M. Phanse, Peter J. Sallaway, James B. Wieser
  • Patent number: 6535054
    Abstract: A band-gap reference circuit with offset cancellation is provided that includes a differential amplifier circuit. The differential amplifier circuit includes a first input node and a second input node. The first input node is operable to receive a first input signal. The second input node is operable to receive a second input signal. The band-gap reference circuit is operable to alternate between a first state and a second state based on a specified duty cycle. The first input node is an inverting node and the second input node is a non-inverting node in the first state, and the first input node is a non-inverting node and the second input node is an inverting node in the second state. The differential amplifier circuit is operable to generate an output signal based on a difference between the first and second input signals.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: March 18, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Vijaya G. Ceekala, Laurence Douglas Lewicki, James B. Wieser