Abstract: The present application describes embodiments of an interface for coupling flash memory and dynamic random access memory (DRAM) in a processing system. Some embodiments include a dedicated interface between a flash memory and DRAM. The dedicated interface is to provide access to the flash memory in response to instructions received over a DRAM interface between the DRAM and a processing device. Some embodiments of a method include accessing a flash memory via a dedicated interface between the flash memory and a dynamic random access memory (DRAM) in response to an instruction received over a DRAM interface between the DRAM and a processing device.

Abstract: The present application describes embodiments of an interface for coupling flash memory and dynamic random access memory (DRAM) in a processing system. Some embodiments include a dedicated interface between a flash memory and DRAM. The dedicated interface is to provide access to the flash memory in response to instructions received over a DRAM interface between the DRAM and a processing device. Some embodiments of a method include accessing a flash memory via a dedicated interface between the flash memory and a dynamic random access memory (DRAM) in response to an instruction received over a DRAM interface between the DRAM and a processing device.

Abstract: The present application describes embodiments of an interface for coupling flash memory and dynamic random access memory (DRAM) in a processing system. Some embodiments include a dedicated interface between a flash memory and DRAM. The dedicated interface is to provide access to the flash memory in response to instructions received over a DRAM interface between the DRAM and a processing device. Some embodiments of a method include accessing a flash memory via a dedicated interface between the flash memory and a dynamic random access memory (DRAM) in response to an instruction received over a DRAM interface between the DRAM and a processing device.

Abstract: Aspects of the present disclosure are directed to a power specification and Network on Chip (NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC with power domains and clock domains. The PS is configured with one or more power domain finite state machines (PDFSMs) that drive signaling for the power domains of the NoC, and is configured to power the NoC elements of the power domain on or off. NoC elements are configured to conduct fencing or draining operations to facilitate the power state transitions.

Abstract: Aspects of the present disclosure are directed to a power specification and Network on Chip (NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC with power domains and clock domains. The PS is configured with one or more power domain finite state machines (PDFSMs) that drive signaling for the power domains of the NoC, and is configured to power the NoC elements of the power domain on or off. NoC elements are configured to conduct fencing or draining operations to facilitate the power state transitions.

Abstract: Aspects of the present disclosure are directed to a power specification and Network on Chip (NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC with power domains and clock domains. The PS is configured with one or more power domain finite state machines (PDFSMs) that drive signaling for the power domains of the NoC, and is configured to power the NoC elements of the power domain on or off. NoC elements are configured to conduct fencing or draining operations to facilitate the power state transitions.

Abstract: Aspects of the present disclosure are directed to a power specification and Network on Chip (NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC with power domains and clock domains. The PS is configured with one or more power domain finite state machines (PDFSMs) that drive signaling for the power domains of the NoC, and is configured to power the NoC elements of the power domain on or off. NoC elements are configured to conduct fencing or draining operations to facilitate the power state transitions.

Abstract: Aspects of the present disclosure are directed to a power specification and Network on Chip (NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC with power domains and clock domains. The PS is configured with one or more power domain finite state machines (PDFSMs) that drive signaling for the power domains of the NoC, and is configured to power the NoC elements of the power domain on or off. NoC elements are configured to conduct fencing or draining operations to facilitate the power state transitions.

Abstract: Aspects of the present disclosure are directed to a power specification and Network on Chip (NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC with power domains and clock domains. The PS is configured with one or more power domain finite state machines (PDFSMs) that drive signaling for the power domains of the NoC, and is configured to power the NoC elements of the power domain on or off. NoC elements are configured to conduct fencing or draining operations to facilitate the power state transitions.

Abstract: Aspects of the present disclosure are directed to a power specification and Network on Chip (NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC with power domains and clock domains. The PS is configured with one or more power domain finite state machines (PDFSMs) that drive signaling for the power domains of the NoC, and is configured to power the NoC elements of the power domain on or off. NoC elements are configured to conduct fencing or draining operations to facilitate the power state transitions.

Abstract: Aspects of the present disclosure are directed to a power specification and Network on Chip (NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC with power domains and clock domains. The PS is configured with one or more power domain finite state machines (PDFSMs) that drive signaling for the power domains of the NoC, and is configured to power the NoC elements of the power domain on or off. NoC elements are configured to conduct fencing or draining operations to facilitate the power state transitions.

Abstract: The present application describes embodiments of an interface for coupling flash memory and dynamic random access memory (DRAM) in a processing system. Some embodiments include a dedicated interface between a flash memory and DRAM. The dedicated interface is to provide access to the flash memory in response to instructions received over a DRAM interface between the DRAM and a processing device. Some embodiments of a method include accessing a flash memory via a dedicated interface between the flash memory and a dynamic random access memory (DRAM) in response to an instruction received over a DRAM interface between the DRAM and a processing device.

Abstract: The present application describes embodiments of an interface for coupling flash memory and dynamic random access memory (DRAM) in a processing system. Some embodiments include a dedicated interface between a flash memory and DRAM. The dedicated interface is to provide access to the flash memory in response to instructions received over a DRAM interface between the DRAM and a processing device. Some embodiments of a method include accessing a flash memory via a dedicated interface between the flash memory and a dynamic random access memory (DRAM) in response to an instruction received over a DRAM interface between the DRAM and a processing device.

Abstract: The present application describes embodiments of an interface for coupling flash memory and dynamic random access memory (DRAM) in a processing system. Some embodiments include a dedicated interface between a flash memory and DRAM. The dedicated interface is to provide access to the flash memory in response to instructions received over a DRAM interface between the DRAM and a processing device. Some embodiments of a method include accessing a flash memory via a dedicated interface between the flash memory and a dynamic random access memory (DRAM) in response to an instruction received over a DRAM interface between the DRAM and a processing device.

Abstract: A two stage rate shaping and scheduling system and method is implemented to control the flow of traffic to at least one output interface. The system and method involves initially queuing incoming packets into type-specific queues and applying individual rate shaping rules to each queue. A first stage arbitration is performed to determine how traffic is queued from the type-specific queues to interface-specific queues. Packets that win arbitration and pass the applied rate shaping rules are queued in interface-specific queues. Rate shaping rules are applied to the interface-specific queues. The interface-specific queues are further distinguished by priority and priority-specific and interface-specific rate shaping rules are applied to each queue. A second stage arbitration is performed to determine how different priority traffic that is targeting the same output interface is dequeued in response to interface-specific requests.

Abstract: A technique for random early drop (RED) with per-hop-behavior (PHB) biasing involves breaking RED parameters into queue-specific parameters and packet-specific parameters. Each queue has associated queue-specific parameters. Each packet has an associated traffic class. The packet-specific parameters are related to the traffic class of the packet. The queue-specific and packet-specific parameters are then both used in RED procedures, thereby providing a PHB bias from using packet-specific parameters. The technique provides for absolute queue size support that can be dynamically changed based upon available memory resource levels.

Abstract: A two stage rate shaping and scheduling system and method is implemented to control the flow of traffic to at least one output interface. The system and method involves initially queuing incoming packets into type-specific queues and applying individual rate shaping rules to each queue. A first stage arbitration is performed to determine how traffic is queued from the type-specific queues to interface-specific queues. Packets that win arbitration and pass the applied rate shaping rules are queued in interface-specific queues. Rate shaping rules are applied to the interface-specific queues. The interface-specific queues are further distinguished by priority and priority-specific and interface-specific rate shaping rules are applied to each queue. A second stage arbitration is performed to determine how different priority traffic that is targeting the same output interface is dequeued in response to interface-specific requests.

Abstract: A technique for random early drop (RED) with per-hop-behavior (PHB) biasing involves breaking RED parameters into queue-specific parameters and packet-specific parameters. Each queue has associated queue-specific parameters. Each packet has an associated traffic class. The packet-specific parameters are related to the traffic class of the packet. The queue-specific and packet-specific parameters are then both used in RED procedures, thereby providing a PHB bias from using packet-specific parameters. The technique provides for absolute queue size support that can be dynamically changed based upon available memory resource levels.

Abstract: A method and apparatus for supplying new requests to a scheduler in an input-buffered multiport switch involve selecting a request that does not target output channels that conflict with output channels targeted by requests that are already accessible to the scheduler. Specifically, target output channels of requests that are presently accessible to the scheduler are identified and compared to target output channels of requests that are included in a queue of next-in-line requests. The queue of next-in-line requests is reviewed and the highest priority request having no conflicting output channels is supplied to the scheduler. By supplying the scheduler with a new request that targets non-conflicting output channels, the scheduler is presented with a wider range of requested output channels from which to choose in each arbitration cycle. In a first embodiment, one, two, or eight ports are connected to each one of four input/output controllers in a switch having a four-channel switch fabric.

Abstract: A method and apparatus for controlling the flow of variable-length packets to a multiport switch involve accessing forwarding information in a memory based at least partially on layer 4 information from a packet and then forwarding the packet only if the packet is within a bandwidth consumption limit that is specified in the forwarding information. In a preferred embodiment, a credit bucket algorithm is used to ensure that packet flows are within specified bandwidth consumption limits. The preferred method for implementing the credit bucket algorithm to control flows of packets involves first receiving a particular packet from a flow and then stripping the layer 2 header information from the packet. The layer 3 and layer 4 information from the packet is then used to look-up flow-specific forwarding and flow control information in a memory that stores a linked list of table entries that includes the fields necessary to implement the credit bucket algorithm.