Abstract: A logic gate is described that implements complex logic within a memory array. The logic gate receives at least three of a first storage cell signal, a second storage cell signal, a first external signal, or a second external signal at a first input circuitry and second input circuitry. The logic gate then performs one of a set of logic functions using the first storage cell signal, the second storage cell signal, the first external signal, or the second external signal. The set of logic functions includes at least one of a matching function, an OR-AND function, or an AND function.

Abstract: A logic gate is described that implements complex logic within a memory array. The logic gate receives at least three of a first storage cell signal, a second storage cell signal, a first external signal, or a second external signal at a first input circuitry and second input circuitry. The logic gate then performs one of a set of logic functions using the first storage cell signal, the second storage cell signal, the first external signal, or the second external signal. The set of logic functions includes at least one of a matching function, an OR-AND function, or an AND function.

Abstract: A logic gate is described that implements complex logic within a memory array. The logic gate receives at least three of a first storage cell signal, a second storage cell signal, a first external signal, or a second external signal at a first input circuitry and second input circuitry. The logic gate then performs one of a set of logic functions using the first storage cell signal, the second storage cell signal, the first external signal, or the second external signal. The set of logic functions includes at least one of a matching function, an OR-AND function, or an AND function.

Abstract: A method and apparatus for using a 2:1 MUX to control read access, data bypass, and page size bypass in a memory array. The mechanism of the present invention reduces the 3:1 MUX normally required to manage these three functions to a 2:1 MUX.

Abstract: A logic gate is described that implements complex logic within a memory array. The logic gate receives at least three of a first storage cell signal, a second storage cell signal, a first external signal, or a second external signal at a first input circuitry and second input circuitry. The logic gate then performs one of a set of logic functions using the first storage cell signal, the second storage cell signal, the first external signal, or the second external signal. The set of logic functions includes at least one of a matching function, an OR-AND function, or an AND function.

Abstract: Disclosed are antiperspirant stick compositions comprising specified amounts of antiperspirant active; carrier oil comprising volatile silicone oil and non-volatile masking oil; structurant comprising fatty alcohol and cosmetically acceptable wax having a melting point of 75 to 95° C., a portion of wax comprises polyethylene in specified amounts. Also disclosed are methods of making such stick compositions, and methods of ameliorating perspiration by the topical application of such compositions to the skin.

Abstract: An apparatus and method is provided that combines both self test and functional features in a single latch circuit, which may be used with an SRAM array and is usefully embodied as an L1-L2 latch. During partial writes from an SRAM array, data bits of unknown state are inhibited from entering the latch circuit, while data for testing is allowed to enter. In one useful embodiment of the invention the latch circuit is used with a mode control that provides mode select signals to operate the latch circuit in one of a plurality of modes, including at least full write and partial write modes. The latch circuit further includes a data hold circuit for selectively receiving and storing data coupled to the latch circuit. A first enabling circuit responsive to the mode select signals enables the hold circuit to receive all the data contained in the array during a full write mode, and further enables the hold circuit to receive only some of the data bits contained in the array during a partial write mode.

Abstract: An apparatus for implementing a least-recently used (LRU) mechanism in a multi-port cache memory includes an LRU array and a shift decoder. The LRU array has multiple entries. The shift decoder includes a shifting means for shifting the entries within the LRU array. The shifting means shifts a current one of the entries and adjacent entries once, and loading new address, in response to a single cache hit in the current one of the entries. The shifting means shifts a current one of the entries and adjacent entries once, and loading an address of only one of multiple requesters into the most-recently used (MRU) entry, in response to multiple cache hits in the current one of the entries. The shifting means shifts all subsequent entries, including the current entries, n times, and loading addresses of all requesters contributed to the multiple cache hits in consecutive entries into the MRU entry and subsequent entries, in response to multiple cache hits in consecutive entries.

Abstract: An apparatus for implementing a least-recently used (LRU) mechanism in a multi-port cache memory includes an LRU array and a shift decoder. The LRU array has multiple entries. The shift decoder includes a shifting means for shifting the entries within the LRU array. The shifting means shifts a current one of the entries and adjacent entries once, and loading new address, in response to a single cache hit in the current one of the entries. The shifting means shifts a current one of the entries and adjacent entries once, and loading an address of only one of multiple requesters into the most-recently used (MRU) entry, in response to multiple cache hits in the current one of the entries. The shifting means shifts all subsequent entries, including the current entries, n times, and loading addresses of all requesters contributed to the multiple cache hits in consecutive entries into the MRU entry and subsequent entries, in response to multiple cache hits in consecutive entries.

Abstract: The present invention is directed to a low residue antiperspirant composition substantially free of water and long chain fatty alcohols which comprises:(a) from about 30% to about 50% of a volatile silicone;(b) from about 5% to about 30% of a particulate antiperspirant active;(c) from about 2% to about 12% of hydrogenated castor oil;(d) from about 8% to about 28% of paraffin; and(e) from about 10% to about 25% of an emollient;wherein the ratio of the paraffin to hydrogenated castor oil is from about 6 to 1 to about 0.85 to 1.