Abstract: A serializer/deserializer interfacing a keypad or keyboard to a processing system is illustrated. However, to minimize wires on intervening cables, a serializer and deserializer is inserted between the processor system and the keypad forming a virtual keypad. The processor scans the deserializer as if it were the keypad and the keypad is scanned by the serializer as if it were the processor. The serializer converts the scanning of the keypad into a serial bit stream and clock that is sent to the deserializer. The deserializer accepts the serial bit stream and reconfigures the data into a response that mimics the response of the physical keypad. In one embodiment an actual second keypad is formed in the deserializer and activated as the first keypad is activated.

Abstract: A system for interleaving high speed data and slower data that is serialized and delivered to a microprocessor. The typical source of the high speed data is a camera and the source of the slower data is a keyboard. The high speed data and the slower data, illustratively, are interfaced with a micro-processor in a parallel fashion. The present invention mirrors the parallel interface to the microprocessor, and mirrors the parallel interface to the sources of the high speed (camera) and slower (keypad) data. The present system formats parallel data from the sources and passes that data in serial form, typically with a clock, on a flexible cable that joins two sections of many cell phones or other hand held devices.

Abstract: A system and process for eliminating a control wire between logic systems that communicate with each other. In one embodiment, a system sends to a receiver a frequency that indicates a first mode. In the first mode a first data type may be sent. When the frequency is changed a second mode is indicated wherein a second data type may be sent. The receiver detects the frequency change and assumes the first or second mode as indicated.

Abstract: A system for interleaving high speed data and slower data that is serialized and delivered to a microprocessor. The typical source of the high speed data is a camera and the source of the slower data is a keyboard. The high speed data and the slower data, illustratively, are interfaced with a micro-processor in a parallel fashion. The present invention mirrors the parallel interface to the microprocessor, and mirrors the parallel interface to the sources of the high speed (camera) and slower (keypad) data. The present system formats parallel data from the sources and passes that data in serial form, typically with a clock, on a flexible cable that joins two sections of many cell phones or other hand held devices.

Abstract: A system and process for eliminating a control wire between logic systems that communicate with each other. In one embodiment, a system sends to a receiver a frequency that indicates a first mode. In the first mode a first data type may be sent. When the frequency is changed a second mode is indicated wherein a second data type may be sent. The receiver detects the frequency change and assumes the first or second mode as indicated.

Abstract: A serializer/deserializer interfacing a keypad or keyboard to a processing system is illustrated. In one application, the processor is arranged to generate keypad scan and input keypad sense lines directly. However, to minimize wires on intervening cables, a serializer and deserializer is inserted between the processor system, the serializer/deserializer forming a virtual keypad. In this case, the processor scans the deserializer as if it were the keypad and the keypad is scanned by the serializer as if it were the processor. However, the serializer converts the scanning of the keypad into a serial bit stream that is sent to the deserializer using only a data line and a clock line. The deserializer accepts the serial bit stream and reconfigures the data into a response that mimics the response of the physical keypad as the computer system scans the virtual keypad, the deserializer.

Abstract: A serializer and a deserializer are disclosed and shown operating singly or as a pair. The invention operates independently from any outside system reference clock. The inventive system provides an internal bit clock that serializes the data when sending and de-serializes the data when receiving. A bit clock or pulse travels with the data word bits to define when a bit is stable. The system uses word boundary bits operating with a bit clock to distinguish different data words, as described in the parent application. The system operates either synchronously or asynchronously with the base computer or other such digital system, including I/O devices. The invention finds use where new data to be sent is strobed into the serializer, but also where a change in the data bit content itself will cause the changed data to be loaded into the serializer and sent bit by bit. The system operates where new data is strobed or loaded by the serializer (not the base computer system) when the last data word has been sent.

Abstract: A bi-directional serializer/deserializer is disclosed using a single bi-directional data line and a single bi-directional clock line. Gated buffers are controlled to operate either sending or receiving data, and a phase locked loop provides a clock to shift data out from a shift register. A reference clock is supplied to the PLL and the PLL generates a synchronous bit clock. The bit clock is sent over the clock line in parallel with the serial data bits, and the PLL bit clock is synchronized to the data bits. The receiving system will use the bit clock to serial load a receiving shift register. When a word is received a word clock is available to inform the receiving system. An embodiment of the system sends data to a receiving system using a clock generated at the sending system.

Abstract: A bi-directional serializer/deserializer is disclosed using a single bi-directional data line and a single bi-directional clock line. Gated buffers are controlled to operate either sending or receiving data, and a phase locked loop provides a clock to shift data out from a shift register. A reference clock is supplied to the PLL and the PLL generates a synchronous bit clock. The bit clock is sent over the clock line in parallel with the serial data bits, and the PLL bit clock is synchronized to the data bits. Two data boundary bits are inserted between the word data bits, the boundary data bits are arranged with a logic level transition between the two data boundary bits. Also, at the boundary of the words during the sending of the two boundary data bits, the synchronous bit clock is arranged to have no logic level transition. The receiving system will use the bit clock to serial load the received word and boundary data bits into a shift register.

Abstract: A translation switch is described with a transfer MOS transistor that connects a first node to second node where the first node is referenced to a higher voltage than is the second. A pseudo-rail generator drives the gate of the MOS transistor and provides a p-rail reference voltage lower in voltage to that of the first node. The generator includes a selectively enabled active clamping circuit that clamps the gate of the MOS transfer transistor to the p-rail potential and sinks current from the p-rail when higher voltages appear on the p-rail to thereby maintain the p-rail at a substantially constant potential.

Abstract: A translation switch circuit for propagating electrical signals between a first node and a second node wherein the power supply associated with the first node is at a potential greater than the power supply associated with the second node. The translation switch circuit includes a pseudorail generator coupled to a transfer transistor disposed between the first and second node. The generator circuit actively clamps the potential associated with the pseudorail. It includes a diode device and a bias pulldown circuit that provides the clamping. The bias pulldown circuit may be a MOS transistor or a MOS transistor in combination with one or more bipolar transistors. The generator circuit also includes a referencing circuit to control the potential associated with the pulldown circuit. That referencing circuit includes in series a pair of diode devices and a resistance.

Abstract: A building component is in the form of an elongate prefabricated cornice to be used in lengths around the top of a wall or walls or a room. The cornice has a mounting part and a facing part. The mounting part has a cross-section with two legs at an angle to each other. The outer edge of each leg terminates in a reflexive bend with the outer portion of the bends inwardly directed. The facing part is a strap of material capable of being snap-fitted into or slid along the mounting part with the inside of each bend serving as a seat to receive a longitudinal edge of the facing part. A corner-piece is provided to join two adjacent lengths of cornice at a corner, the corner-piece being in two parts having a wall-mountable angle bracket and a correspondingly angled cornice part to be secured thereto.