Abstract: The use of ultrasonic transducers installed in utility meters is provided for the detection of fluid leaks in a conduit. Such transducers are normally used to transmit acoustic waves in order to measure the velocity of fluid flow, but it is disclosed that such transducers are also capable of detecting leak noises in addition to such transmitted acoustic waves.

Abstract: The use of ultrasonic transducers installed in utility meters is provided for the detection of fluid leaks in a conduit. Such transducers are normally used to transmit acoustic waves in order to measure the velocity of fluid flow, but it is disclosed that such transducers are also capable of detecting leak noises in addition to such transmitted acoustic waves.

Abstract: Devices to detect utility theft are provided, as well as methods of their use. The devices are utility meters that have a positioning detector; a microprocessor connected to receive readings from the positioning detector; a memory storage device in communication with the microprocessor, and at least one power source to provide power to the microprocessor and the memory storage device. Combining positioning readings with theft detection algorithms allows increased accuracy in the automated detection of theft, even when grid power is not available to power the accelerometer or compass.

Abstract: A fixed network for automatically reading a utility meter system has been developed. The network includes multiple meter interface units (MIUs) that each collect data from a designated utility meter. The collected data is transmitted to a primary data collector. The network includes multiple data collectors and each MIU identifies its own primary data collector based on signal quality between the collector and the MIU. The network includes a central host computer that is used to receive the collected data from the primary data collectors.

Abstract: A fixed network for automatically reading a utility meter system has been developed. The network includes multiple meter interface units (MIUs) that each collect data from a designated utility meter. The collected data is transmitted to a primary data collector. The network includes multiple data collectors and each MIU identifies its own primary data collector based on signal quality between the collector and the MIU. The network includes a central host computer that is used to receive the collected data from the primary data collectors.

Abstract: A shipping box or platform having a bottom with rails extending outwardly from the sides thereof adjacent the bottom is locked down onto the floor of an aircraft by a pair of spaced apart elongated locking members mounted on the floor. The distance between the locking members limits the width of the bottom of the shipping box or platform. In order to increase the size of the box or platform, the side walls extend outwardly beyond the width of the bottom. The lockdown rails are thus recessed beneath the side walls of the box or platform.

Abstract: A shipping box having a bottom with rails extending outwardly from the sides thereof adjacent the bottom is locked down onto the floor of an aircraft by a pair of spaced apart elongated locking members mounted on the floor. The distance between the locking members limits the width of the bottom of the shipping box. In order to increase the size of the box, the side walls extend outwardly beyond the width of the bottom. The lockdown rails are thus recessed beneath the side walls of the box.

Abstract: The present invention is a method and apparatus to program a flash memory cell in an analog storage array. A read circuit reads a cell voltage of a flash memory cell. A comparator compares the read cell voltage with an input voltage representing an analog signal. The comparator generates first and second comparison results. A programming circuit generates a first program pulse corresponding to a first amplitude to iteratively program the flash memory cell based on the first comparison result. The programming circuit generates a second program pulse corresponding to a second amplitude less than the first amplitude to iteratively program the flash memory cell based on the first and second comparison results.

Abstract: This invention provides column redundancy circuits in a storage array, which circuits are used in a non-volatile memory chip to increase the production yield due to manufacturing defects. The invention includes a scheme to latch and transfer the redundancy information, a redundancy logic circuit, a redundancy column driver, an array architecture with column redundancy, a scheme to program and read the column redundancy memory cells, a scheme to multiplex the fuses, and circuits to use an out-of-bound address as a column redundancy enable/disable signal.

Abstract: A trimbit circuit for flash memory integrated circuits is described. The trimbit circuit is used to store the addresses of bad rows and/or columns in flash memory arrays. Furthermore the trimbit circuit is used to store the trimbits for trimable circuits in the integrated circuit, i.e. voltage references, precision oscillator, etc. The invention includes a row of flash memory trimcells and a trimcell differential amplifier circuit. The trimcell differential amplifier circuit can serially shift in trimbits into a latch and serially shift out trimbits without having to program the flash memory trimcells. The final settings of the trimbits can be programmed by means of a high voltage buffer. A non-overlapping clock generator and additional logic is also included to control the circuit.

Abstract: An analog recording and playback system using non-volatile flash memory. An array of flash memory cells is used to store an analog signal and retrieve the stored analog signal on a real-time basis. A plurality of column driver circuits are coupled to the columns of flash memory cells for simultaneous programming and reading. A programming algorithm is used to write the analog signal within an operating range of the flash memory cells since the operating range may shift due to process variations. The system includes trimbit circuits to provide a trimmable initial programming voltage, programming step, programming current, read current, and select gate voltage. The system further includes a Serial Peripheral Interface ("SPI") that interfaces with a host microcontroller. The host microcontroller can send a number of commands to the system through the SPI for efficient message management. These commands include the basic commands to record or playback and various addressing and message cueing options.

Abstract: A trimbit circuit for flash memory integrated circuits is described. The trimbit circuit is used to store the addresses of bad rows and/or columns in flash memory arrays. Furthermore the trimbit circuit is used to store the trimbits for trimable circuits in the integrated circuit, i.e. voltage references, precision oscillator, etc. The invention includes a row of flash memory trimcells and a trimcell differential amplifier circuit. The trimcell differential amplifier circuit can serially shift in trimbits into a latch and serially shift out trimbits without having to program the flash memory trimcells. The final settings of the trimbits can be programmed by means of a high voltage buffer. A non-overlapping clock generator and additional logic is also included to control the circuit.

Abstract: This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.

Abstract: This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.

Abstract: This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.

Abstract: A voltage switching circuit is described that includes a switching circuit for selectively coupling a first voltage to an output of the switching circuit. The first voltage has a voltage level substantially lower than zero volts. A control circuit is coupled to the switching circuit for controlling the switching circuit to couple the first voltage to the output by generating a second voltage having a voltage level lower than that of the first voltage from a third voltage having a voltage level substantially higher than zero volts.

Abstract: An integrated circuit which provides an arrangement by which the source of voltage for erasing the flash EEPROM memory array is detected and, if the source is a charge pump, the current provided is held to a constant lower value while, if the source is an external high voltage source, then the current is allowed to flow freely without regulation except by the size of a field effect transistor device in the path from the source of voltage to the memory array. In this manner, the circuitry is adapted to function with either internal or external power sources without paying a performance penalty for either type of operation.

Abstract: A novel nonvolatile memory cell structure is provided using a non-self aligned CMOS process with two independent N+ implants using a two or a three polysilicon layer technology that allows in-circuit electrical erase and reprogramming together with reduction in cell size requirement. The novel memory cell is implemented with a merged transistor structure having an access transistor and a programmable transistor. The memory cell is constructed by having the control gate, formed of a first polysilicon layer, covering a portion of the channel length between drain and source to form the access portion of the merged transistors, and a floating gate formed of a second polysilicon layer overlapping a second portion of the channel length to form the programmable transistor portion of the merged transistor. Such merged transistor structure is equivalent to two transistors in series, a programmable transistor in series with an access transistor.

Abstract: An integrated circuit which provides an arrangement by which the source of voltage for erasing the flash EEPROM memory array is detected and, if the source is a charge pump, the current provided is held to a constant lower value while, if the source is an external high voltage source, then the current is allowed to flow freely without regulation except by the size of a field effect transistor device in the path from the source of voltage to the memory array. In this manner, the circuitry is adapted to function with either internal or external power sources without paying a performance penalty for either type of operation.

Abstract: A nonvolatile memory residing on a single substrate is described. The nonvolatile memory includes a memory array having at least a memory cell. The memory cell includes a drain region, a source region, a control gate, and a floating gate. A drain programming voltage generation circuit is coupled to a programming voltage source and the drain region of the memory cell for providing a drain programming voltage to the drain region of the memory cell during programming of the memory cell. A control circuit is coupled to the drain programming voltage generation circuit for causing the drain programming voltage to vary with respect to a programming ability of the memory cell such that the memory cell is programmed to be within a predetermined range of a predetermined threshold voltage with a predetermined gate programming voltage for a predetermined programming time.