Abstract: A transceiver includes an integrated circuit that enables board-level configuration of an on-chip or external transmit/receive switch. The transceiver uses a high-Q matching network, at least part of which is external, that improves receiver performance; increases transmit power while allowing for configuration of the same chip to use an internal TR switch, or external TR switch by changing connection at the board level rather than the chip level.

Abstract: A USB isolator integrated circuit, including: an isolation barrier disposed between an upstream portion and a downstream portion of the integrated circuit to provide galvanic isolation therebetween; a first USB 2.0 interface configured to receive and transmit USB 2.0 compliant signals between the upstream portion of the integrated circuit and an upstream USB entity; a second USB 2.0 interface configured to receive and transmit USB 2.0 compliant signals between the downstream portion of the integrated circuit and a downstream USB entity; a plurality of signal coupling components configured to allow communication between the upstream portion and the downstream portion of the integrated circuit to allow the upstream USB entity and the downstream USB entity to communicate therebetween using a USB 2.0 protocol while maintaining the galvanic isolation therebetween; and the upstream and downstream portions of the integrated circuit including respective modules configured to automatically detect a USB 2.

Abstract: A transceiver includes an integrated circuit that enables board-level configuration of an on-chip or external transmit/receive switch. The transceiver uses a high-Q matching network, at least part of which is external, that improves receiver performance; increases transmit power while allowing for configuration of the same chip to use an internal TR switch, or external TR switch by changing connection at the board level rather than the chip level.