Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Abstract: An apparatus and method are described for comparing elements between two immediate values. For example, a method according to one embodiment includes the following operations: reading values of a first set of elements stored in a first immediate value, each element having a defined element position in the first immediate value; comparing each element from the first set of elements with each of a second set of elements stored in a second immediate value; counting the number of times the value of each element of the first set of elements is found in the second set of elements to arrive at a final count for each element of the first set of elements; and transferring the final count for each element to a third immediate value, wherein the final count is stored in an element position in the third immediate value corresponding to the defined element position in the first immediate value.

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Abstract: Method, apparatus, and program means for performing a packed multiply high with round and shift operation. The method of one embodiment comprises receiving a first operand having a first set of L data elements. A second operand having a second set of L data elements is received. L pairs of data elements are multiplied together to generate a set of L products. Each of the L pairs includes a first data element from the first set of L data element and a second data element from a corresponding data element position of the second set of L data elements. Each of the L products are rounded to generate L rounded values. Each of said L rounded values are scaled to generate L scaled values. Each of the L scaled values are truncated for storage at a destination. Each truncated value is to be stored at a data element position corresponding to its pair of data elements.

Abstract: Pixel values of an image are loaded into main memory and cache of a computer system. Two different instructions are used to load pixel values of the image from the cache to a set of registers in a processor of the system. A first one is used when loading an operand (containing pixel values) that is aligned with a cache line boundary of the cache. A second instruction is to be used when loading an operand (containing pixel values) that is not aligned with the cache line boundary. The second instruction can execute a cache line split without a significant performance penalty relative to execution of the first instruction. Other embodiments are also described and claimed.

Abstract: A system and a method of automatically prioritizing and analyzing performance data for one or more system configurations are provided. Performance data is obtained about a system using a first tool. The performance data is sorted by a number of contexts, each context divided into a number of sub-contexts. The performance data for at least one sub-context is automatically prioritized using a pre-determined criteria. An insight is obtained using a second tool for at least one sub-context based on the prioritized performance data. An advice associated with that insight is obtained using the second tool.

Abstract: Method, apparatus, and program means for performing a packed multiply high with round and shift operation. The method of one embodiment comprises receiving a first operand having a first set of L data elements. A second operand having a second set of L data elements is received. L pairs of data elements are multiplied together to generate a set of L products. Each of the L pairs includes a first data element from the first set of L data element and a second data element from a corresponding data element position of the second set of L data elements. Each of the L products are rounded to generate L rounded values. Each of said L rounded values are scaled to generate L scaled values. Each of the L scaled values are truncated for storage at a destination. Each truncated value is to be stored at a data element position corresponding to its pair of data elements.

Abstract: A system and a method of automatically prioritizing and analyzing performance data for one or more system configurations are provided. Performance data is obtained about a system using a first tool. The performance data is sorted by a number of contexts, each context divided into a number of sub-contexts. The performance data for at least one sub-context is automatically prioritized using a pre-determined criteria. An insight is obtained using a second tool for at least one sub-context based on the prioritized performance data. An advice associated with that insight is obtained using the second tool.

Abstract: Perforations and cracks in wellbore liners or casings may be temporarily or permanently covered by a radially-expansible, coiled sleeve member formed by a sheet of elastically-deflectable material such as stainless steel which is coiled and placed in a cylinder which may be conveyed into a well to a working position for deployment of the sleeve to expand into engagement with the casing wall to block the perforations or cracks. The cylinder includes a sleeve ejecting piston which may be urged to rapidly eject the sleeve from the cylinder by pressure fluid conveyed to the cylinder by coilable tubing or by a gas-generating charge material electrically connected to an E-line which also may be used to deploy the cylinder into its working position in the well.

Abstract: Fractures are initiated or extended within an earth formation from a well which includes a tubing string extending to a wellbore space adjacent the fracture zone from a conventional wellhead. Carbon dioxide, nitrogen or a similar highly expansible fluid is pumped into the wellbore space and/or at least a portion of the tubing string at a pressure greater than the fluid critical pressure and greater than the fracture initiation or extension pressure required in the formation zone. A perforating gun is fired or a shear disk is actuated to release the expansible fluid to flow into the formation at an initial velocity and kinetic energy which substantially exceeds that which is obtained with water or similar conventional fracturing fluids so as to initiate or extend hydraulic fractures with a minimum radius of curvature with respect to the wellbore.

Abstract: Hydraulic fractures are initiated or extended into fluid-producing earth formations from a cased well by filling a space within the casing adjacent the formation zone of interest with liquid which extends into a tubing string and forming a pressure gas charged portion of the tubing string by introducing pressure gas or liquid into the tubing string to compress a column of gas therein to a pressure which exceeds the formation fracture breakdown pressure. By perforating the casing or, if perforations already exist, releasing a frangible disk type closure interposed in the tubing string, the gas charge in the tubing string forces fluid into the formation at sustained pressure and flow conditions not attainable by surface pumped fracture fluids.

Abstract: Water injection wells are fractured by a proppant-laden fracturing fluid to create a propped fracture and wherein the proppant-laden fluid is followed by injection of a substantially proppant-free fluid so that the near wellbore portion of the fracture is free of proppant to minimize pressure drop during water injection and to produce higher injection rates for a given injection pressure. The fracture treatment may include the use of viscous fracturing and displacement fluids which are degraded by the injection of acid-bearing fluids at the end of the fracture treatment cycle. Stimulation or displacement liquid (water) injection may commence immediately after the fracture treatment and may be alternated with miscible gas injection.