Patents by Inventor James C. Bowman

James C. Bowman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12106621
    Abstract: Methods and apparatus to monitor and manage loading docks and facility operations are disclosed. An example apparatus includes a data analyzer to: monitor first data indicating whether a truck trailer is present at a dock of the material handling facility; and monitor second data indicating a condition associated with a door at the dock, the second data being different than the first data. The apparatus further includes a notification generator to generate a notification based on the first data and the second data.
    Type: Grant
    Filed: March 9, 2019
    Date of Patent: October 1, 2024
    Assignee: RITE-HITE HOLDING CORPORATION
    Inventors: James C. Boerger, John Jeffers, Richard Mews, Adam White, Kyle Wurster, Viswa Teja Yerramsetty, Kenneth C. Bowman, Brian J. Peschel
  • Patent number: 8947444
    Abstract: A data structure that includes pointers to vertex attributes and primitive descriptions is generated and then processed within a general processing cluster. The general processing cluster includes a vertex attribute fetch unit that fetches from memory vertex attributes corresponding to the vertices defined by the primitive descriptions.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: February 3, 2015
    Assignee: NVIDIA Corporation
    Inventors: Ziyad S. Hakura, Emmett M. Kilgariff, Michael C. Shebanow, James C. Bowman, Philip Browning Johnson, Johnny S. Rhoades, Rohit Gupta
  • Patent number: 8941653
    Abstract: One embodiment of the present invention sets forth a technique for rendering graphics primitives in parallel while maintaining the API primitive ordering. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives concurrently to multiple rasterizers at rates of multiple primitives per clock while maintaining the primitive ordering for each pixel. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: January 27, 2015
    Assignee: NVIDIA Corporation
    Inventors: Steven E. Molnar, Emmett M. Kilgariff, John S. Rhoades, Timothy John Purcell, Sean J. Treichler, Ziyad S. Hakura, Franklin C. Crow, James C. Bowman
  • Patent number: 8810592
    Abstract: One embodiment of the present invention sets forth a technique for providing primitives and vertex attributes to the graphics pipeline. A primitive distribution unit constructs the batches of primitives and writes inline attributes and constants to a vertex attribute buffer (VAB) rather than passing the inline attributes directly to the graphics pipeline. A batch includes indices to attributes, where the attributes for each vertex are stored in a different VAB. The same VAB may be referenced by all of the vertices in a batch or different VABs may be referenced by different vertices in one or more batches. The batches are routed to the different processing engines in the graphics pipeline and each of the processing engines reads the VABs as needed to process the primitives. The number of parallel processing engines may be changed without changing the width or speed of the interconnect used to write the VABs.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: August 19, 2014
    Assignee: NVIDIA Corporation
    Inventors: Ziyad S. Hakura, James C. Bowman, Jimmy Earl Chambers, Philip Browning Johnson, Philip Payman Shirvani
  • Patent number: 8760455
    Abstract: One embodiment of the present invention sets forth a technique for reducing overhead associated with transmitting primitive draw commands from memory to a graphics processing unit (GPU). Command pairs comprising an end draw command and a begin draw command associated with a conventional graphics application programming interface (API) are selectively replaced with a new construct. The new construct is a reset topology index, which implements a combined function of the end draw command and begin draw command. The new construct improves efficiency by reducing total data transmitted from memory to the GPU.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: June 24, 2014
    Assignee: NVIDIA Corporation
    Inventors: Jerome F. Duluk, Jr., Thomas Roell, James C. Bowman
  • Publication number: 20140152652
    Abstract: One embodiment of the present invention sets forth a technique for rendering graphics primitives in parallel while maintaining the API primitive ordering. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives concurrently to multiple rasterizers at rates of multiple primitives per clock while maintaining the primitive ordering for each pixel. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.
    Type: Application
    Filed: November 18, 2013
    Publication date: June 5, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Steven E. MOLNAR, Emmett M. KILGARIFF, John S. RHOADES, Timothy John PURCELL, Sean J. TREICHLER, Ziyad S. HAKURA, Franklin C. CROW, James C. BOWMAN
  • Patent number: 8587581
    Abstract: One embodiment of the present invention sets forth a technique for rendering graphics primitives in parallel while maintaining the API primitive ordering. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives concurrently to multiple rasterizers at rates of multiple primitives per clock while maintaining the primitive ordering for each pixel. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: November 19, 2013
    Assignee: Nvidia Corporation
    Inventors: Steven E. Molnar, Emmett M. Kilgariff, Johnny S. Rhoades, Timothy John Purcell, Sean J. Treichler, Ziyad S. Hakura, Franklin C. Crow, James C. Bowman
  • Patent number: 8564616
    Abstract: One embodiment of the invention sets forth a mechanism for compiling a vertex shader program into two portions, a culling portion and a shading portion. The culling portion of the compiled vertex shader program specifies vertex attributes and instructions of the vertex shader program needed to determine whether early vertex culling operations should be performed on a batch of vertices associated with one or more primitives of a graphics scene. The shading portion of the compiled vertex shader program specifies the remaining vertex attributes and instructions of the vertex shader program for performing vertex lighting and performing other operations on the vertices in the batch of vertices. When the compiled vertex shader program is executed by graphics processing hardware, the shading portion of the compiled vertex shader is executed only when early vertex culling operations are not performed on the batch of vertices.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: October 22, 2013
    Assignee: Nvidia Corporation
    Inventors: Ziyad S. Hakura, John Erik Lindholm, Emmett M. Kilgariff, Robert Ohannessian, Scott R. Whitman, James C. Bowman, Patrick R. Brown, Ross A. Cunniff
  • Patent number: 8558842
    Abstract: One embodiment of the present invention sets forth a technique for detecting duplicate vertex indices in parallel and batching indices defining multiple primitives for parallel primitive processing. A lookback cache breaks the dependent loop for the miss processing. Because each index is compared to all previous indices (duplicate or not), each index is not dependent on whether the previous indices have hit or missed. This allows the comparison operation that detects the duplicate vertex indices to be fully pipelined. The duplicate vertex indices are removed to reduce the number of indices that define the primitives in the batch. Multiple, independent rasterizer units operate concurrently on the different batches of graphics primitives to render multiple primitives per system clock.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: October 15, 2013
    Assignee: NVIDIA Corporation
    Inventors: Philip B. Johnson, James C. Bowman
  • Patent number: 8542247
    Abstract: One embodiment of the invention sets forth a mechanism for compiling a vertex shader program into two portions, a culling portion and a shading portion. The culling portion of the compiled vertex shader program specifies vertex attributes and instructions of the vertex shader program needed to determine whether early vertex culling operations should be performed on a batch of vertices associated with one or more primitives of a graphics scene. The shading portion of the compiled vertex shader program specifies the remaining vertex attributes and instructions of the vertex shader program for performing vertex lighting and performing other operations on the vertices in the batch of vertices. When the compiled vertex shader program is executed by graphics processing hardware, the shading portion of the compiled vertex shader is executed only when early vertex culling operations are not performed on the batch of vertices.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: September 24, 2013
    Assignee: Nvidia Corporation
    Inventors: Ziyad S. Hakura, John Erik Lindholm, Emmett M. Kilgariff, Robert Ohannessian, Scott R. Whitman, James C. Bowman, Patrick R. Brown, Ross A. Cunniff
  • Patent number: 8237725
    Abstract: A vertex cache within a graphics processor is configured to operate as a conventional round-robin streaming cache when per-vertex state changes are not used and is configured to operate as a random access storage buffer when per-vertex state changes are used. Batches of vertices that define primitives and state changes are output to parallel processing units for processing according to vertex shader program. In addition to allowing per-vertex state changes, the vertex cache is configured to store vertices for primitive topologies that use anchor points, such as triangle strips, line loops, and polygons.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: August 7, 2012
    Assignee: NVIDA Corporation
    Inventors: James C. Bowman, Dane T. Mrazek, Sameer M. Gauria
  • Publication number: 20110109638
    Abstract: One embodiment of the present invention sets forth a technique for reducing overhead associated with transmitting primitive draw commands from memory to a graphics processing unit (GPU). Command pairs comprising an end draw command and a begin draw command associated with a conventional graphics application programming interface (API) are selectively replaced with a new construct. The new construct is a reset topology index, which implements a combined function of the end draw command and begin draw command. The new construct improves efficiency by reducing total data transmitted from memory to the GPU.
    Type: Application
    Filed: October 4, 2010
    Publication date: May 12, 2011
    Inventors: Jerome F. DULUK, JR., Thomas Roell, James C. Bowman
  • Publication number: 20110102448
    Abstract: One embodiment of the present invention sets forth a technique for providing primitives and vertex attributes to the graphics pipeline. A primitive distribution unit constructs the batches of primitives and writes inline attributes and constants to a vertex attribute buffer (VAB) rather than passing the inline attributes directly to the graphics pipeline. A batch includes indices to attributes, where the attributes for each vertex are stored in a different VAB. The same VAB may be referenced by all of the vertices in a batch or different VABs may be referenced by different vertices in one or more batches. The batches are routed to the different processing engines in the graphics pipeline and each of the processing engines reads the VABs as needed to process the primitives. The number of parallel processing engines may be changed without changing the width or speed of the interconnect used to write the VABs.
    Type: Application
    Filed: September 30, 2010
    Publication date: May 5, 2011
    Inventors: Ziyad S. HAKURA, James C. Bowman, Jimmy Earl Chambers, Philip Browning Johnson, Philip Payman Shirvani
  • Publication number: 20110090220
    Abstract: One embodiment of the present invention sets forth a technique for rendering graphics primitives in parallel while maintaining the API primitive ordering. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives concurrently to multiple rasterizers at rates of multiple primitives per clock while maintaining the primitive ordering for each pixel. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.
    Type: Application
    Filed: October 15, 2009
    Publication date: April 21, 2011
    Inventors: Steven E. Molnar, Emmett M. Kilgariff, Johnny S. Rhoades, Timothy John Purcell, Sean J. Treichler, Ziyad S. Hakura, Franklin C. Crow, James C. Bowman
  • Patent number: 7796137
    Abstract: Disclosed are an apparatus, a system, a method, a graphics processing unit (“GPU”), a computer device, and a computer medium to implement a pool of independent enhanced tags to, among other things, decouple a dependency between tags and cachelines. In one embodiment, an enhanced tag-based cache structure includes a tag repository configured to maintain a pool of enhanced tags. Each enhanced tag can have a match portion configured to form an association between the enhanced tag and an incoming address. Also, an enhanced tag can have a data locator portion configured to locate a cacheline in the cache in response to the formation of the association. The data locator portion enables the enhanced tag to locate multiple cachelines. Advantageously, the enhanced tag-based cache structure can be formed to adjust the degree of reusability of the enhanced tags independent from the degree of latency tolerance for the cacheline repository.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: September 14, 2010
    Assignee: NVIDIA Corporation
    Inventors: Dane T. Mrazek, Sameer M. Gauria, James C. Bowman
  • Patent number: 7797258
    Abstract: A graphics system includes a transposer. A read scheduler utilizes a minimum cost analysis to schedule a read transfer order for the transposer to minimize the total number of passes required to process a set of input vectors.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: September 14, 2010
    Assignee: NVIDIA Corporation
    Inventors: James C. Bowman, Dane T. Mrazek, Sameer M. Gauria
  • Patent number: 7755631
    Abstract: Disclosed are an apparatus, a method, a programmable graphics processing unit (“GPU”), a computer device, and a computer medium to facilitate, among other things, the generation of parallel data streams to effect parallel processing in at least a portion of a graphics pipeline of a GPU. In one embodiment, an input of the apparatus receives graphics elements in a data stream of graphics elements. The graphics pipeline can use the graphics elements to form computer-generated images. The apparatus also can include a transposer configured to produce parallel attribute streams. Each of the parallel attribute streams includes a type of attribute common to the graphics elements. In one embodiment, the transposer can be configured to convert at least a portion of the graphics pipeline from a single data stream to multiple data streams (e.g., executable by multiple threads of execution) while reducing the memory size requirements to implement such a conversion.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: July 13, 2010
    Assignee: Nvidia Corporation
    Inventors: Dane T. Mrazek, Sameer M. Gauria, James C. Bowman
  • Patent number: 7701459
    Abstract: A graphics system has parallel processing units that do not share vertex information. The graphics system constructs independent batches of work for the parallel processing units in which each batch of work has a list of vertices for a set of primitives.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: April 20, 2010
    Assignee: NVIDIA Corporation
    Inventors: Dane T. Mrazek, James C. Bowman, Sameer M. Gauria
  • Patent number: D1037289
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: July 30, 2024
    Assignee: RITE-HITE HOLDING CORPORATION
    Inventors: James C. Boerger, Richard Mews, Kenneth C. Bowman
  • Patent number: D1045898
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: October 8, 2024
    Assignee: RITE-HITE HOLDING CORPORATION
    Inventors: James C. Boerger, Richard Mews, Kenneth C. Bowman