Abstract: A crest factor reduction (CRF) circuit may include a scaler configured to receive the input signal and generate a scaled input signal. A clipping circuit may be configured to receive the input signal and generate a clipped input signal. A negator circuit may be configured to receive the clipped input signal and generate a negated clipped input signal. A first summer may be configured to sum the scaled input signal and the negated clipped input signal to generate a summed signal. A first digital filter may be configured to receive the summed signal and provide a first digital filter output. A second digital filter may be configured to receive the clipped input signal and provide a second digital filter output. A multiplexer may be configured to receive the first digital filter output and the second digital filter output and generate an output signal.

Abstract: A crest factor reduction (CRF) circuit may include a scaler configured to receive the input signal and generate a scaled input signal. A clipping circuit may be configured to receive the input signal and generate a clipped input signal. A negator circuit may be configured to receive the clipped input signal and generate a negated clipped input signal. A first summer may be configured to sum the scaled input signal and the negated clipped input signal to generate a summed signal. A first digital filter may be configured to receive the summed signal and provide a first digital filter output. A second digital filter may be configured to receive the clipped input signal and provide a second digital filter output. A multiplexer may be configured to receive the first digital filter output and the second digital filter output and generate an output signal.

Abstract: Embodiments of the present invention are directed to improved battery packaging designs. The battery pack design may include a battery cell, a plurality of transistors, and a controller. The transistors may be coupled to the terminals of the battery cell in an H-bridge configuration. The controller may control the transistors to bypass the battery cell based on the current flowing between the output terminals of the battery pack. In such a manner, the controller may prevent damage to the battery cell and improve the overall safety of the battery pack in hazardous conditions. Moreover, the design may allow for more efficient charging/discharging of the cells that are most ready to accept/supply current.

Abstract: Embodiments of the present invention relate to a battery stack controller system. The system may include a plurality of battery cell stages with cell controller systems (as described above with respect to the first embodiment). The system may also include a stack controller to send charge/discharge commands to the battery stack via a communication network. The stack controller may send the commands to the battery stack based on the requirements of a load or the state of the battery cell stages. The battery cell stages may either comply with the commands or send the commands to neighboring cells via the communication network.

Abstract: Embodiments of the present invention are directed to a battery stack with a leapfrogging communication network. Each cell stage may include a controller, a transmitter, and a pair of receivers. The cell stage in the battery stack may be coupled to the closest two preceding battery cell stages in the stack. In this manner, each cell stage may be able to determine if a fault is present in an immediately preceding cell stage in the stack by monitoring the first preceding cell stage and the second preceding cell stage. If discharge/charge commands transmitted by the second preceding cell stage are not reaching the battery cell stage at issue, the controller may determine that there is a fault in the first preceding cell stage and discharge/charge the cell stage based on the commands transmitted by the second preceding cell stage.

Abstract: Embodiments of the present invention are directed to an improved battery packaging design. The battery pack design may include a battery cell, a plurality of transistors, and a controller. The transistors may be coupled to the terminals of the battery cell in an H-bridge configuration. The controller may control the transistors to bypass the battery cell based on the current flowing between the output terminals of the battery pack. In such a manner, the controller may prevent damage to the battery cell and improve the overall safety of the battery pack in hazardous conditions.

Abstract: Embodiments of the present invention may provide a signal processing circuit that may comprises an analog-to-digital converter (ADC), and an output restriction circuit. The output restriction circuit may reduce the accuracy of the digital output of the ADC when signal content exceeds a pre-determined spectrum mask in an undesirable band. In one embodiment, the input signal spectrum may be actively monitored and when the input spectrum is inconsistent with an intended application, the output resolution may be restricted, for example, by truncating least significant bits (LSBs) of the digital output or adding digital noise.

Abstract: Embodiments of the present invention relate to a battery stack controller system. The system may include a plurality of battery cell stages with cell controller systems (as described above with respect to the first embodiment). The system may also include a stack controller to send charge/discharge commands to the battery stack via a communication network. The stack controller may send the commands to the battery stack based on the requirements of a load or the state of the battery cell stages. The battery cell stages may either comply with the commands or send the commands to neighboring cells via the communication network.

Abstract: Embodiments of the present invention are directed to improved battery packaging designs. The battery pack design may include a battery cell, a plurality of transistors, and a controller. The transistors may be coupled to the terminals of the battery cell in an H-bridge configuration. The controller may control the transistors to bypass the battery cell based on the current flowing between the output terminals of the battery pack. In such a manner, the controller may prevent damage to the battery cell and improve the overall safety of the battery pack in hazardous conditions. Moreover, the design may allow for more efficient charging/discharging of the cells that are most ready to accept/supply current.

Abstract: Embodiments of the present invention are directed to an improved battery packaging design. The battery pack design may include a battery cell, a plurality of transistors, and a controller. The transistors may be coupled to the terminals of the battery cell in an H-bridge configuration. The controller may control the transistors to bypass the battery cell based on the current flowing between the output terminals of the battery pack. In such a manner, the controller may prevent damage to the battery cell and improve the overall safety of the battery pack in hazardous conditions.

Abstract: Embodiments of the present invention are directed to a battery stack with a leapfrogging communication network. Each cell stage may include a controller, a transmitter, and a pair of receivers. The cell stage in the battery stack may be coupled to the closest two preceding battery cell stages in the stack. In this manner, each cell stage may be able to determine if a fault is present in an immediately preceding cell stage in the stack by monitoring the first preceding cell stage and the second preceding cell stage. If discharge/charge commands transmitted by the second preceding cell stage are not reaching the battery cell stage at issue, the controller may determine that there is a fault in the first preceding cell stage and discharge/charge the cell stage based on the commands transmitted by the second preceding cell stage.

Abstract: Embodiments of the present invention may provide a signal processing circuit that may comprises an analog-to-digital converter (ADC), and an output restriction circuit. The output restriction circuit may reduce the accuracy of the digital output of the ADC when signal content exceeds a pre-determined spectrum mask in an undesirable band. In one embodiment, the input signal spectrum may be actively monitored and when the input spectrum is inconsistent with an intended application, the output resolution may be restricted, for example, by truncating least significant bits (LSBs) of the digital output or adding digital noise.

Abstract: A communication system includes a multi-channel signal regulation system that limits an aggregate signal in response to an indication that the aggregate signal exceeds a threshold value. The aggregate signal is formed from a combination of the input signals.

Abstract: Upconverter structures are provided that generate selected television signals with digital upconverters that are coupled between analog-to-digital converters and digital-to-analog converters. Embodiments of the digital upconverters generally include at least one digital quadrature modulator that facilitates the conversion of digital intermediate-frequency sequences to digital broadcast sequences and further include at least one digital interpolation filter that facilitates the conversion of an input sample rate to an output sample rate.

Abstract: Bias controllers are provided which alter a bias control signal so that a bias signal (e.g., a current signal) of an electronic network rapidly responds to increases in the rate-of-change of the network's analog input signal. This enhances the linearity of a system that includes the electronic network. Subsequent decreases in the rate-of-change are sensed and a decrease of the bias control signal is then paced at a rate selected to ignore short-term rate-of-change variations (e.g., modulation variations) but follow longer-term rate-of-change reductions to thereby enhance system efficiency without sacrificing system linearity.

Abstract: Channel use in a wireless communication system is monitored for each radio frequency channel spanning a broad allocated bandwidth simultaneously. A transmission having signals in channels spanning the bandwidth is broadband downconverted in analog before being transformed to produce an instantaneous representation of signal levels in each channel. The instantaneous representation is stored. In addition, a statistic characterizing historical use of at least one of the channels in the bandwidth is calculated from the instantaneous representation.

Abstract: A robust interpolator performs internal data correction to avoid catastrophic errors. The interpolator includes a filter connected to an integrator by both a feedforward path and an element that increases the data rate of the output of the filter. The filter processes signals arriving at an input data rate to produce differentiated data and filtered data. The filtered data represents an output of the integrator in the absence of error. The integrator receives the differentiated data from the element at a data rate higher than the input data rate, and receives the filtered data via the feedforward path. A transmultiplexer producing a wideband signal from two or more narrowband signals employs the interpolator to increase the data rate of its output.