Abstract: The present invention relates to a digital-to-digital code converter, or decimator, which implements sinc.sup.3 processing. The input signal (X) to the code converter comprises a series of groups, each group including a series of N digital sample values occurring at high rate (1/.tau.) which are converted within the converter, using sinc.sup.3 processing, into a single digital value occurring at, for example, a (1/N).tau. rate for delivery to the converter output (Y). The code converter comprises three processing stages in cascade, where each stage includes separate accumulation means, each accumulation means arranged to add, during each series of N input sample values, the signal value received by that stage from the next preceding stage.

Abstract: Digital signals are processed by a first accumulator to generate most significant bits which represent the signal to be converted but with truncation noise. The error signals from the first accumulator are processed by a second accumulator to generate a second set of most significant bits which are used to remove the truncation noise. The most significant bits from the second accumulator are converted to analog form, differentiated and then combined with the most significant bits from the first accumulator after being converted from digital to analog form. The combined signal is then amplified and filtered.

Abstract: A terrestrial light beam communication system is described for compatible utilization with existing radio transmission systems. The transmitter (FIG. 4) utilizes aiming means (41 and 42) to control the aim of the transmitted light beam. The receiver employs an array of detectors (FIG. 5) from which a circuit (FIG. 6) determines the position of the received light beam. The position of the received light beam is used to control the position of the transmitted light beam from which control signals are developed to maintain the aim of the transmitted light beam to combat the occurrence of ongoing fluctuations in the vertical deflection experienced by the transmitted light beam.

Abstract: A digital filter includes a pair of serially connected second order sections (200 and 260), each of which includes delay elements arranged to store the number of bits contained in two complete input words. Each filter section also includes simple logic (220, 230, 270 and 280) comprising adder circuits and inverters but no multipliers. The logic combines outputs from the delay element with the filter input to form an intermediate signal which is applied to the input of the delay element. The intermediate signal is also combined with yet other outputs from the delay element to form the filter output. To eliminate clocking complexity within the filter, the logic is not preset or cleared between each input word. Instead, the word length is intentionally increased, and the sign bit of each intermediate word is intentionally repeated as the word is processed in the filter, the extra bits acting as an inter-word buffer and serving to protect against spurious overflow and limit cycle oscillations.

Abstract: An interpolator is arranged to form an increment for each interpolation interval by dividing the difference between the interpolator input and output by a number N indicating the desired number of output samples in the interval. During each interval, the increment is repeatedly added to each output to form the next output.

Abstract: A digital-to-digital converter is arranged to provide "decimated" output samples at rate f.sub.0, each of which represent a group of input samples received at a rate m times greater. Each output is generated using overlapped triangularly weighted accumulation on an interval including 2m preceding input samples. The samples near the beginning and end of each accumulation interval receive the smallest weight, and the samples at the middle of the interval receive the greatest weight. The converter is achievable in integrated circuit form using first and second serially connected accumulators, the first accumulating m input samples without weighting and the second being used to weight the samples so that the first receives m times the weight of the last sample. The output of the first accumulator is increased in scale by the factor "m" and the output of the second accumulator subtracted therefrom. The difference is delayed so that the next m samples may be accumulated.