Abstract: An approach is provided in which an endianness violation detection sub-system detects endianness violations between hardware units. The endianness violation detection sub-system tracks memory operations performed by multiple hardware units via debug channels and generates lookup table entries that are stored in a lookup table. When the endianness violation detection sub-system detects endianness relevant load attributes of a load operation that are different than corresponding endianness relevant store attributes of a store operation, the endianness violation detection sub-system generates an endianness violation. In one embodiment, the endianness violation detection sub-system identifies an endianness violation when the endianness violation detection sub-system detects a difference in the byte ordering type between a hardware unit performing a store operation and a hardware unit performing a load operation.

Abstract: A processing system includes a processor configured to execute a plurality of instructions corresponding to a task, wherein the plurality of instructions comprises a resource transfer instruction to indicate a transfer of processing operations of the task from the processor to a different resource and a hint instruction which precedes the resource transfer instruction by a set of instructions within the plurality of instructions. A processor task scheduler is configured to schedule tasks to the processor, wherein, in response to execution of the hint instruction of the task, the processor task scheduler finalizes selection of a next task and loads a context of the selected next task into a background register file. The loading occurs concurrently with execution of the set of instructions between the hint instruction and resource transfer instruction, and, after loading is completed, the processor switches to the selected task in response to the resource transfer instruction.

Abstract: A processing system includes a processor pipeline, a detector circuit, and a task scheduler. The detector circuit includes a basic block detector circuit to determine that the processor pipeline received a first instruction of a first instance of a basic block, and to determine that a last-in-order instruction of the first instance of the basic block is a resource switch instruction (RSWI), and an indicator circuit to provide an indication in response to determining that the processor pipeline received the first instruction of a second instance of the basic block. The task scheduler initiates a resource switch, in response to the indication, at a time subsequent to the first instruction being received that is based on a cycle count that indicates a first number of processor cycles between receiving the first instruction and receiving the RSWI.

Abstract: A processing system includes a processor pipeline, a detector circuit, and a task scheduler. The detector circuit includes a basic block detector circuit to determine that the processor pipeline received a first instruction of a first instance of a basic block, and to determine that a last-in-order instruction of the first instance of the basic block is a resource switch instruction (RSWI), and an indicator circuit to provide an indication in response to determining that the processor pipeline received the first instruction of a second instance of the basic block. The task scheduler initiates a resource switch, in response to the indication, at a time subsequent to the first instruction being received that is based on a cycle count that indicates a first number of processor cycles between receiving the first instruction and receiving the RSWI.

Abstract: A method for pipelined data stream processing of packets includes determining a task to be performed on each packet of a data stream, the task having a plurality of task portions including a first task portion. Determining the first task portion is to process a first packet. In response to determining a first storage location stores a first barrier indicator, enabling the first task portion to process the first packet and storing a second barrier indicator at the first location. Determining the first task portion is to process a second next-in-order packet. In response to determining the first location stores the second barrier indicator, preventing the first task portion from processing the second packet. In response to a first barrier clear indicator, storing the first barrier indicator at the first location, and in response, enabling the first task portion to process the second packet.

Abstract: A method for pipelined data stream processing of packets includes determining a task to be performed on each packet of a data stream, the task having a plurality of task portions including a first task portion. Determining the first task portion is to process a first packet. In response to determining a first storage location stores a first barrier indicator, enabling the first task portion to process the first packet and storing a second barrier indicator at the first location. Determining the first task portion is to process a second next-in-order packet. In response to determining the first location stores the second barrier indicator, preventing the first task portion from processing the second packet. In response to a first barrier clear indicator, storing the first barrier indicator at the first location, and in response, enabling the first task portion to process the second packet.

Abstract: An approach is provided in which an endianness violation detection sub-system detects endianness violations between hardware units. The endianness violation detection sub-system tracks memory operations performed by multiple hardware units via debug channels and generates lookup table entries that are stored in a lookup table. When the endianness violation detection sub-system detects endianness relevant load attributes of a load operation that are different than corresponding endianness relevant store attributes of a store operation, the endianness violation detection sub-system generates an endianness violation. In one embodiment, the endianness violation detection sub-system identifies an endianness violation when the endianness violation detection sub-system detects a difference in the byte ordering type between a hardware unit performing a store operation and a hardware unit performing a load operation.

Abstract: A processing system includes a processor configured to execute a plurality of instructions corresponding to a task, wherein the plurality of instructions comprises a resource transfer instruction to indicate a transfer of processing operations of the task from the processor to a different resource and a hint instruction which precedes the resource transfer instruction by a set of instructions within the plurality of instructions. A processor task scheduler is configured to schedule tasks to the processor, wherein, in response to execution of the hint instruction of the task, the processor task scheduler finalizes selection of a next task and loads a context of the selected next task into a background register file. The loading occurs concurrently with execution of the set of instructions between the hint instruction and resource transfer instruction, and, after loading is completed, the processor switches to the selected task in response to the resource transfer instruction.

Abstract: A set of instructions executable at an integrated circuit is partitioned into multiple instruction blocks. A first and second instruction block are executed multiple times, including a first execution and a second execution. The first execution of the first instruction block is associated with a first set of executions, and the first execution of the second instruction block is associated with a second set of executions. A first amount of energy consumption representative of a member of the first set of executions is determined, and a second amount of energy consumption representative of a member of the second set of executions is determined. The first amount of energy is assigned to each member of the first set, and the second amount of energy is assigned to each member of the second set, and used to determine a total amount of energy consumption associated with execution of the set of instructions.

Abstract: A set of instructions executable at an integrated circuit is partitioned into multiple instruction blocks. A first and second instruction block are executed multiple times, including a first execution and a second execution. The first execution of the first instruction block is associated with a first set of executions, and the first execution of the second instruction block is associated with a second set of executions. A first amount of energy consumption representative of a member of the first set of executions is determined, and a second amount of energy consumption representative of a member of the second set of executions is determined. The first amount of energy is assigned to each member of the first set, and the second amount of energy is assigned to each member of the second set, and used to determine a total amount of energy consumption associated with execution of the set of instructions.

Abstract: Generating a hashed value of the program counter in a data processing system. The hashed value can be used for prefetching in the data processing system. In some examples, the hashed value is used to identify whether a load instruction associated with the hashed value has an address that is part of a strided stream in an address stream. In some examples, the hashed value is a subset of bits of the bits of the program counter. In other examples, the hashed value may be derived in other ways from the program counter.

Abstract: A first prefetch engine from a first plurality of prefetch engines is allocated to a first load instruction in response to a buffer miss of an iteration of the first load instruction in a program stream. The first plurality of prefetch engines include prefetch engines for prefetching data from memory to a buffer based on a predicted stride. A second prefetch engine from a second plurality of prefetch engines is allocated to the first load instruction in response to the buffer miss. The second plurality of prefetch engines include prefetch engines for prefetching data from memory to the buffer based on an instruction loop representative of a sequence of instructions that affect an address value associated with an allocated load instruction. One of the first or second prefetch engines is deallocated if the other prefetch engine achieves a prefetch performance greater than a first threshold value.

Abstract: The Dynamic Bendloss Measuring Device allows easy, repeatable determination of the bend sensitivity of a single-mode optical fiber by subjecting the fiber to dynamically changing bend angles under varying degrees of tension and bend diameters. It utilizes a swing arm capable of sweeping an arc subtending a range of angles at any given bend diameter and fiber tension and calculating the bendloss from the light attenuation at each degree of the range. The varying bend diameters are provided by pins of diverse diameters that are singly inserted into an adjustably-sized aperture while the variation in the applied tension can be effected by changing the input current setting in the tension assembly. With each new pin and tension setting, the swing arm sweeps through the pre-selected range of bend angles, resulting in varying degrees of attenuation of light.

Abstract: A neuron (100) has a null-inhibiting function so that null inputs do not affect the output of the neuron (100) or updating of its weights. The neuron (100) provides a net value based on a sum of products of each of several inputs, and corresponding weight and null values, and provides an output in response to the net value. A neural network (40) which uses such a neuron (100) has a first segmented layer (41) in which each segment (50-52) corresponds to a manufacturing process step (60-62). Each segment of the first layer (41) receives as inputs measured values associated with the process step (60-62). A second layer (42) connected to the first layer (4l), is non-segmented to model the entire manufacturing process (80). The first (41) and second (42) layers are both unsupervised and competitive. A third layer (43) connected to the second layer (42) then estimates parameters of the manufacturing process (80) and is unsupervised and noncompetitive.

Abstract: A turns count anomaly detector for detecting any irregularities in the pat count of a fiber optic able from fiber optic dispensers. The detector receives an input from an infrared source and receiver that monitors a fiber optic cable during fiber optic cable payout at speeds up to 700 feet per second. A turns count pulse electronics circuitry supplies an input to a turns count anomaly detector. The turns count anomaly detector is comprised of transistor transistor logic one-shot configured as a negative recovery monostable multivibrator. Input to the one-shot is received from a pulse conditioning circuit comprised of a logic signal inverter and a digital flip-flop. The input to the pulse conditioning circuit is the output from the turns count pulse electronics.

Abstract: An Infrared Fiber Optic Distribution Sensor (IFODS) and control system is ed in a non-contact method for ensuring that a fiber optic cable is unwound from a supply spool at a nominal angle to thereby reduce the twist and stress imparted to the cable. The system is mounted to a fiber optic winding machine platform for an automatic fiber winding system (AFWS). The AFWS is used to precision wind fiber optic dispensers for the Non-Line of Sight (NLOS) weapon system as well as the Naval Weapons Center's SKYRAY program. The IFODS uses pairs of infrared sources and receivers mounted directly across from each other and perpendicular to the plane of the fiber to sense the position of the fiber. Three pairs of sources/receivers are utilized. They are arranged so that the axis of each pair is offset from the center pair by 0.06 inches. If the fiber optic cable breaks the beam of the top pair the distribution motor will drive the supply spool down until he fiber breaks the beam of the middle pair.