Patents by Inventor James C. Hunt

James C. Hunt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8065572
    Abstract: An integrated circuit configured for at-speed scan testing of memory arrays. The integrated circuit includes a scan chain having a plurality of serially coupled scan elements, wherein a subset of the plurality of scan elements are coupled to provide signals to a memory array. Each scan element of the subset of the plurality of scan elements includes a flip flop having a data input, and a data output coupled to a corresponding input of the memory array, and selection circuitry configured to, in an operational mode, couple a data path to the data input, and further configured to, in a scan mode, couple to the data input one of a scan input, the data output, and a complement of the data output. The scan elements of the subset support at-speed testing of a memory array coupled thereto.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: November 22, 2011
    Assignee: Oracle America, Inc.
    Inventors: Thomas A. Ziaja, Murali Gala, Paul J. Dickinson, Karl P. Dahlgren, David L. Curwen, Oliver Caty, Steven C. Krow-Lucal, James C. Hunt, Poh-Joo Tan
  • Publication number: 20100332924
    Abstract: An integrated circuit configured for at-speed scan testing of memory arrays. The integrated circuit includes a scan chain having a plurality of serially coupled scan elements, wherein a subset of the plurality of scan elements are coupled to provide signals to a memory array. Each scan element of the subset of the plurality of scan elements includes a flip flop having a data input, and a data output coupled to a corresponding input of the memory array, and selection circuitry configured to, in an operational mode, couple a data path to the data input, and further configured to, in a scan mode, couple to the data input one of a scan input, the data output, and a complement of the data output. The scan elements of the subset support at-speed testing of a memory array coupled thereto.
    Type: Application
    Filed: June 30, 2009
    Publication date: December 30, 2010
    Inventors: Thomas A. Ziaja, Murali Gala, Paul J. Dickinson, Karl P. Dahlgren, David L. Curwen, Oliver Caty, Steven C. Krow-Lucal, James C. Hunt, Poh-Joo Tan
  • Patent number: 5519715
    Abstract: A method is disclosed for loading a compiled test program into a microprocessor's internal caches and then controlling the execution of that program. Initially, the microprocessor's internal clock is disabled. Then for each memory location specified in the compiled program, the memory content associated with that location is loaded into the appropriate microprocessor cache. This is accomplished in two primary steps. First, the memory content is shifted into positions on the pins of the microprocessor by a boundary scan shift operation via an IEEE 1149.1 interface. Second, after the pins have the appropriate bit values for the current memory content, an external clock supplies the microprocessor with clock cycles that are then used by the microprocessor to control the loading of data/instructions from the pins into the appropriate data or instruction cache.
    Type: Grant
    Filed: January 27, 1995
    Date of Patent: May 21, 1996
    Assignee: Sun Microsystems, Inc.
    Inventors: Hong Hao, Richard F. Avra, James C. Hunt, Kanti Bhabuthmal