Abstract: A Vector Network Analyzer is equipped with receivers for measuring a1, b1, a2 and b2 and which can each be tuned to track either the RF signal (F1) applied to the FTD or to the IF (F2) produced by the FTD. Additional forward side and reverse side mixers are provided and are driven by the auxiliary LO for the FTD. The additional mixers can be located in the RF/IF path, such that there is a sequential double conversion of the RF/IF: one by the auxiliary LO followed by another conversion of those results by the main LO. The additional mixers could also be located it the LO path, such that the main LO is first converted to an image involving the auxiliary LO, and the RF/IF is then subsequently converted using that image as an ‘artificial’ LO. During a forward direction measurement of an FTD, the applied RF signal (F1) is converted to the IF with the additional forward side mixers that feeds the receivers for a1 and b1.

Abstract: A Trellis decoder allows for real time decoding of high rate input data more than 10 MHz, with a compact layout and without the need to generate very high speed clocks, by use of a branch metric generator feeding multiple parallel Add/Compare/Select modules, which in turn feed a traceback processor using pre-traceback shift registers and traceback memory. The decoder performs n-state Trellis decoding in real time while simultaneously de-interleaving a multiplexed data stream. The architecture can be expanded to provide programmable length traceback in a fixed number of clock cycles. The invention performs de-interleaving in parallel with the Trellis decoding, and symbols coming out of the decoder need no further processing for de-interleaving. Moreover, the invention allows complete traceback in one symbol period at video rates without the need for very high speed clocks or multi-read port memories. Programmability allows for flexible tradeoff of output error rate and traceback memory space.

Abstract: The invention presents a method of frame synchronization of Digital Video Broadcasting (DVB) data using a temporary storage area (regfile) of substantially smaller dimension than the repetition rate of the sync pattern. Synchronization is achieved by detecting the sync pattern by correlation and determining if the pattern has a fixed repetitive separation. The synchronization scheme of the invention is simple and easily implementable as an integrated circuit, using software and a microprocessor, or as discrete circuitry.