Patents by Inventor James C Matayabas

James C Matayabas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11881440
    Abstract: Microelectronic devices, assemblies, and systems include a microelectronic die and composite material to conduct heat from the microelectronic die such that the composite material includes polymer chains chemically bonded to fill particles having a hexagonal lattice of carbon atoms such as graphene sheet fill particles and/or carbon nanotube fill particles.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: January 23, 2024
    Assignee: Intel Corporation
    Inventors: Marely E. Tejeda Ferrari, Taylor Gaines, Elah Bozorg-Grayeli, James C. Matayabas, Jr.
  • Patent number: 11562940
    Abstract: An apparatus is provided which comprises: a die comprising an integrated circuit, a first material layer comprising a first metal, the first material layer on a surface of the die, and extending at least between opposite lateral sides of the die, a second material layer comprising a second metal over the first material layer, and a third material layer comprising silver particles and having a porosity greater than that of the second material layer, the third material layer between the first material layer and the second material layer. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: January 24, 2023
    Assignee: Intel Corporation
    Inventors: Elizabeth Nofen, James C. Matayabas, Jr., Yawei Liang, Yiqun Bai
  • Patent number: 11545407
    Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: January 3, 2023
    Assignee: Intel Corporation
    Inventors: Kumar Abhishek Singh, Omkar Karhade, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Aastha Uppal, Debendra Mallik, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Manish Dubey, Ravindranath Mahajan, Ram Viswanath, James C. Matayabas, Jr.
  • Patent number: 11404349
    Abstract: In some embodiments a semiconductor die package includes a package substrate, a plurality of dies each attached to the package substrate, a layer of a thermally conducting sintered paste over the top of each die, a layer of flexible polymer thermal interface material over the sintered paste, and a heat spreader over and thermally connected to the polymer thermal interface material.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Nachiket R. Raravikar, Ravindranath V. Mahajan, Robert L. Sankman, James C. Matayabas, Jr., Ken P. Hackenberg, Nayandeep K. Mahanta, David D. Olmoz
  • Patent number: 11189574
    Abstract: A microelectronic package may be fabricated with a microelectronic substrate, a microelectronic die electrically attached to the microelectronic substrate, and an electromagnetic interference shield layer contacting one or both of the microelectronic substrate and the microelectronic die, wherein the electromagnetic interference shield layer has an electrical conductivity between about 10,000 siemens per meter and 100,000 siemens per meter. The specific range of electrical conductivity results in electromagnetic fields either generated by the microelectronic die or generated by components external to the microelectronic package scattering within the electromagnetic interference shield layer and attenuating. Thus, the electromagnetic interference shield layer can prevent electromagnetic field interference without the need to be grounded.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: November 30, 2021
    Assignee: Intel Corporation
    Inventors: Li-Sheng Weng, Chung-Hao Chen, James C. Matayabas, Jr., Min Keen Tang
  • Publication number: 20210265238
    Abstract: Microelectronic devices, assemblies, and systems include a microelectronic die and composite material to conduct heat from the microelectronic die such that the composite material includes polymer chains chemically bonded to fill particles having a hexagonal lattice of carbon atoms such as graphene sheet fill particles and/or carbon nanotube fill particles.
    Type: Application
    Filed: February 21, 2020
    Publication date: August 26, 2021
    Applicant: INTEL CORPORATION
    Inventors: Marely E. Tejeda Ferrari, Taylor Gaines, Elah Bozorg-Grayeli, James C. Matayabas, JR.
  • Publication number: 20210118809
    Abstract: A microelectronic package may be fabricated with a microelectronic substrate, a microelectronic die electrically attached to the microelectronic substrate, and an electromagnetic interference shield layer contacting one or both of the microelectronic substrate and the microelectronic die, wherein the electromagnetic interference shield layer has an electrical conductivity between about 10,000 siemens per meter and 100,000 siemens per meter. The specific range of electrical conductivity results in electromagnetic fields either generated by the microelectronic die or generated by components external to the microelectronic package scattering within the electromagnetic interference shield layer and attenuating. Thus, the electromagnetic interference shield layer can prevent electromagnetic field interference without the need to be grounded.
    Type: Application
    Filed: May 31, 2017
    Publication date: April 22, 2021
    Applicant: Intel Corporation
    Inventors: Li-Sheng Weng, Chung-Hao Chen, James C. Matayabas, Jr., Min Keen Tang
  • Publication number: 20200350229
    Abstract: An integrated circuit package includes a first die and second die above a substrate, and a vapor chamber above at least one of the first and second die. A vapor space within the vapor chamber is separated into at least a first section and a second section. The first section may be over the first die, and the second section may be over the second die, for example. The structure separating the first and second sections at least partly restricts flow of vapor between the first and second sections, thereby preventing or reducing thermal cross talk between the first and second dies. In some cases, an anisotropic thermal material is above one of the first or second die, wherein the anisotropic thermal material has substantially higher thermal conductivity in a direction of a heat sink than a thermal conductivity in a direction of a section of the vapor chamber.
    Type: Application
    Filed: April 30, 2019
    Publication date: November 5, 2020
    Applicant: Intel Corporation
    Inventors: Je-Young Chang, James C. Matayabas, JR., Zhimin Wan, Kyle Arrington
  • Publication number: 20200286806
    Abstract: An apparatus is provided which comprises: a die comprising an integrated circuit, a first material layer comprising a first metal, the first material layer on a surface of the die, and extending at least between opposite lateral sides of the die, a second material layer comprising a second metal over the first material layer, and a third material layer comprising silver particles and having a porosity greater than that of the second material layer, the third material layer between the first material layer and the second material layer. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: March 8, 2019
    Publication date: September 10, 2020
    Applicant: Intel Corporation
    Inventors: Elizabeth Nofen, James C. Matayabas, JR., Yawei Liang, Yiqun Bai
  • Publication number: 20200286809
    Abstract: Multi-die semiconductor device packages include a solder thermal interface material for a processor device, and a carbon-pad thermal interface material for a high-bandwidth memory device. Disparate dice are packaged against a heat sink on the device backsides, and on a semiconductor package substrate on the device active surfaces and metallizations.
    Type: Application
    Filed: March 5, 2019
    Publication date: September 10, 2020
    Inventors: Shushan Gong, James C. Matayabas, JR.
  • Publication number: 20200273811
    Abstract: IC package including a material preform comprising graphite. The material preform may have a thermal conductivity higher than that of other materials in the package and may therefore mitigate the formation of hot spots within an IC die during device operation. The preform may have high electrical conductivity suitable for EMI shielding. The preform may comprise a graphite sheet that can be adhered to a package assembly with an electrically conductive adhesive, applied, for example over an IC die surface and a surrounding package dielectric material. Electrical interconnects of the package may be coupled to the graphite sheet as an EMI shield. The package preform may be grounded to a reference potential through electrical interconnects of the package, which may be further coupled to a system-level ground plane. System-level thermal solutions may interface with the package-level graphite sheet.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 27, 2020
    Applicant: Intel Corporation
    Inventors: Debendra Mallik, Mitul Modi, Sanka Ganesan, Edvin Cetegen, Omkar Karhade, Ravindranath Mahajan, James C. Matayabas, Jr., Jan Krajniak, Kumar Singh, Aastha Uppal
  • Publication number: 20200227332
    Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.
    Type: Application
    Filed: January 10, 2019
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventors: Kumar Abhishek Singh, Omkar Karhade, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Aastha Uppal, Debendra Mallik, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Manish Dubey, Ravindranath Mahajan, Ram Viswanath, James C. Matayabas, JR.
  • Patent number: 10586779
    Abstract: Embodiments describe high aspect ratio and fine pitch interconnects for a semiconductor package, such as a package-on-package structure. In an embodiment, the interconnects are formed with a no-slump solder paste. In an embodiment, the no-slump solder paste is printed in an uncured state, and is then cured with a liquid phase sintering process. After being cured, the no-slump solder paste will not reflow at typical processing temperatures, such as those below approximately 400° C. According to embodiments, the no-slump solder paste includes Cu particles or spheres, a solder matrix component, a polymeric delivery vehicle, and a solvent. In an embodiment, the liquid phase sintering produces a shell of intermetallic compounds around the Cu spheres. In an embodiment, the sintering process builds a conductive metallic network through the no-slump solder paste.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: March 10, 2020
    Assignee: Intel Corporation
    Inventors: Nachiket R. Raravikar, James C. Matayabas, Jr., Akshay Mathkar
  • Patent number: 10580717
    Abstract: A multiple chip package is described with multiple thermal interface materials. In one example, a package has a substrate, a first semiconductor die coupled to the substrate, a second semiconductor die coupled to the substrate, a heat spreader coupled to the die, wherein the first die has a first distance to the heat spreader and the second die has a second distance to the heat spreader, a first filled thermal interface material (TIM) between the first die and the heat spreader to mechanically and thermally couple the heat spreader to the die, and a second filled TIM between the second die and the heat spreader to mechanically and thermally couple the heat spreader to the second die.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Boxi Liu, Hemanth K. Dhavaleswarapu, Syadwad Jain, James C. Matayabas, Jr.
  • Publication number: 20190267306
    Abstract: In some embodiments a semiconductor die package includes a package substrate, a plurality of dies each attached to the package substrate, a layer of a thermally conducting sintered paste over the top of each die, a layer of flexible polymer thermal interface material over the sintered paste, and a heat spreader over and thermally connected to the polymer thermal interface material.
    Type: Application
    Filed: December 7, 2016
    Publication date: August 29, 2019
    Applicant: Intel Corporation
    Inventors: Nachiket R. RARAVIKAR, Ravindranath V. MAHAJAN, Robert L. SANKMAN, James C. MATAYABAS, Jr., Ken P. HACKENBERG, Nayandeep K. MAHANTA, David D. OLMOZ
  • Publication number: 20190099777
    Abstract: A fluid applicator configured to apply a fluid to at least one substrate feature includes a manifold plate having an inflow orifice and a manifold reservoir. A distributor plate is coupled with the manifold plate. The distributor plate includes a distributor surface extending across the manifold reservoir, and a distributor port array spread across the distributor surface and in communication with the manifold reservoir. A compressible reticulated media is configured for applying the fluid to the at least one substrate feature. The compressible reticulated media includes an input interface coupled along the distributor surface, and a substrate interface having an applicator profile corresponding to a feature profile of the at least one substrate feature. Reticulations extend from the input interface to the substrate interface, and the reticulations are distributed across the substrate interface.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Ken P. Hackenberg, Nachiket R. Raravikar, James C. Matayabas, JR., Elizabeth Nofen, Seth B. Reynolds, Amram Eitan, Nisha Ananthakrishnan
  • Publication number: 20190099776
    Abstract: A fluid applicator configured to apply a fluid to at least one substrate feature. The includes compressible reticulated media including an input interface configured for coupling with a fluid reservoir, and a substrate interface having an applicator profile corresponding to a feature profile of the at least one substrate feature. Reticulations extend from the input interface to the substrate interface, and the reticulations are distributed across the applicator profile. The compressible reticulated media includes filling and dispensing configurations. In the dispensing configuration the substrate interface is configured for engagement with the at least one substrate feature, the compressible reticulated media is compressed, and according to the compression the fluid is applied across the feature profile. In the filling configuration the compressible reticulated media is configured for expansion relative to the dispensing configuration, and the fluid infiltrates the reticulations according to the expansion.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Ken P. Hackenberg, Nachiket R. Raravikar, James C. Matayabas, JR., Elizabeth Nofen, Nisha Ananthakrishnan, Manabu Nakagawasai, Yoshihiro Tomita
  • Publication number: 20190006259
    Abstract: Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a first die disposed on a substrate and a second die disposed adjacent the first die on the substrate. A cooling solution is attached to the substrate, wherein a rib extends from a central region of the cooling solution and is attached to the substrate. The rib is disposed between the first die and the second die.
    Type: Application
    Filed: June 29, 2017
    Publication date: January 3, 2019
    Applicant: Intel Corporation
    Inventors: Dinesh Padmanabhan Ramalekshmi Thanu, Wei Hu, James C. Matayabas, JR., Baris Bicen, Luke J. Garner, Hemanth Dhavaleswarapu
  • Publication number: 20180374776
    Abstract: A multiple chip package is described with multiple thermal interface materials. In one example, a package has a substrate, a first semiconductor die coupled to the substrate, a second semiconductor die coupled to the substrate, a heat spreader coupled to the die, wherein the first die has a first distance to the heat spreader and the second die has a second distance to the heat spreader, a first filled thermal interface material (TIM) between the first die and the heat spreader to mechanically and thermally couple the heat spreader to the die, and a second filled TIM between the second die and the heat spreader to mechanically and thermally couple the heat spreader to the second die.
    Type: Application
    Filed: January 11, 2016
    Publication date: December 27, 2018
    Inventors: Boxi LIU, Hemanth K. DHAVALESWARAPU, Syadwad JAIN, James C. MATAYABAS, Jr.
  • Publication number: 20180323130
    Abstract: An adhesive polymer thermal interface material is described with sintered fillers for thermal conductivity in micro-electronic packaging. Embodiments include a polymer thermal interface material (PTIM) with sinterable thermally conductive filler particles, a dispersant, and a silicone polymer matrix.
    Type: Application
    Filed: December 22, 2015
    Publication date: November 8, 2018
    Inventors: Boxi LIU, Syadwad JAIN, Jelena CULIC-VISKOTA, Nachiket R. RARAVIKAR, James C. MATAYABAS, Jr.