Abstract: A headstage for a Neural Data Acquisition System is shown and described. In one embodiment, the headstage includes at least one Input Pre-amplifier, and a multiplexer (MUX) for multiplexing at least one channel. In one embodiment, the input filter of the Input Pre-amplifier is tuned by adjusting the gate voltage of a transistor operating in sub-threshold mode.

Abstract: An enhanced frame buffet pixel circuit with two control transistors and a separate capacitor put in as a memory capacitor before the memory transistor yields a high contrast ratio by removing induced charge and solving a charge sharing problem between the memory capacitor and the liquid crystal display (LCD) capacitor. The memory transistor may be made of either CMOS or PMOS. The frame buffer pixel can be used to drive binary displays which expresses ON and OFF only if a comparator is put in after the pixel electrode circuit to represent gray levels with reduced sub-frame frequency.

Abstract: A headstage for a Neural Data Acquisition System is shown and described. In one embodiment, the headstage includes at least one Input Pre-amplifier, and a multiplexer (MUX) for multiplexing at least one channel. In one embodiment, the input filter of the Input Pre-amplifier is tuned by adjusting the gate voltage of a transistor operating in sub-threshold mode.

Abstract: A Wireless Neural Data Acquisition System for increased power efficiency, compact size, robust signaling and reliable transmission is shown and described. In one embodiment, the system includes a headstage, an RF receiver, an analog-to-digital converter, a digital signal processor, and a communication interface. The headstage includes at least one input pre-amplifier high-pass filter and amplifier, a multiplexer (MUX), an RF Modulator comprising a voltage control oscillator (VCO), a transmitting antenna, and a power supply. The RF receiver includes at least one receiving antenna, at least one bandpass filter, at least one amplifier, at least one attenuator, and an FM Demodulator.

Abstract: Neurochip for Neuroprosthetic Control. According to one embodiment, a neural spike detection system is provided. The neural spike detection system can include a signal receiver operable to receive a plurality of neural signals including neural spikes. The system can also include a neural spike detector adapted to communicate with the signal receiver and detect neural spikes in the plurality of neural signals. Further, the system can include a transmitter connected to the neural spike detector and operable to transmit an information signal when a neural spike is detected.

Abstract: An enhanced frame buffer pixel circuit with two control transistors and a separate capacitor put in as a memory capacitor before the memory transistor yields a high contrast ratio by removing induced charge and solving a charge sharing problem between the memory capacitor and the liquid crystal display (LCD) capacitor. The memory transistor may be made of either CMOS or PMOS. The frame buffer pixel can be used to drive binary displays which expresses ON and OFF only if a comparator is put in after the pixel electrode circuit to represent gray levels with reduced sub-frame frequency.

Abstract: An enhanced frame buffer pixel circuit with two control transistors and a separate capacitor put in as a memory capacitor before the memory transistor yields a high contrast ratio by removing induced charge and solving a charge sharing problem between the memory capacitor and the liquid crystal display (LCD) capacitor. The memory transistor may be made of either CMOS or PMOS. The frame buffer pixel can be used to drive binary displays which expresses ON and OFF only if a comparator is put in after the pixel electrode circuit to represent gray levels with reduced sub-frame frequency.

Abstract: A sigma-delta analog-to-digital (A/D) converter has an analog modulator, and an adjustable reference voltage circuit that provides a reference voltage to the analog modulator along a feedback path during A/D conversion. The reference voltage circuit includes a reference voltage generator that provides a plurality of positive and negative polarity signals to a gain multiplexer. The gain multiplexer selectively supplies a pair of positive and negative polarity signals to the analog modulator based on a select signal produced by a gain register and a microprocessor interface bus that together allow adjustment of the range of operation and performance of the sigma-delta A/D converter. This adjustment is made based on a particular application in which the converter is implemented; as the relative input power of an input signal changes, the sigma-delta A/D converter as dynamically adjusted, realizes higher performance.

Abstract: A circuit and method for compensating for the output phase delay of an external clock signal utilizes a phase-locked loop that includes an output port of an integrated circuit device. In the phase-locked loop, a phase detecting circuit compares the external clock signal with an output signal from the output port, producing a phase error signal. The phase error signal is applied to a skew compensator to generate an internal clock signal. The internal clock signal is fed back through the output port to the phase detecting circuit. Clock jitter is reduced by reducing the gain of the skew compensator after a phase lock condition occurs in the compensation circuit.