Abstract: A technique is described that reduces parasitic losses in circuits used to drive current through a load. An example of a system according to the technique includes four switches in series with five pins such that one pin is connected to ground. An example of an apparatus according to the technique may include four switches in series with two switches connected to ground and to a load and two switches connected to a power source. An example of a method according to the technique involves producing a voltage waveform having three phases.

Abstract: A method of driving a lamp that uses a DC to AC inverter that is connected to a primary winding of a transformer is disclosed. The inverter frequency is variable, and in one embodiment, may be controlled by a voltage controlled oscillator. Circuitry is included that monitors the phase relationship between a voltage across a secondary of the transformer and a current through the primary of the transformer. The circuitry monitors the phase relationship and adjusts the inverter frequency, such as by adjusting voltage controlled oscillator, so that the phase relationship is maintained at a predetermined relationship.

Abstract: The present disclosure introduces a simple method and apparatus for converting DC power to AC power for driving discharge lamps such as a cold cathode fluorescent lamp (CCFL), an external electrode fluorescent lamp (EEFL), or a flat fluorescent lamp (FFL). Among other advantages, the invention allows the proper protection under short circuit conditions for applications where the normal lamp current is greater than safe current limit.

Abstract: A technique for driving one or more EEFLs, having first and second ends, in a bank of EEFLs involves driving the EEFLs at both the first and second ends. In a non-limiting embodiment a device constructed according to the technique includes a bank of EEFLs connected in parallel. The device further includes a first transformer, wherein a secondary winding of the first transformer is coupled to the first end of the bank of EEFLs. The device further includes a second transformer, wherein a secondary winding of the second transformer is coupled to the second end of the bank of EEFLs.

Abstract: The base of a thermal shutdown bipolar transistor having a V.sub.BE(on) which decreases with increasing temperature is biased with a bias voltage V.sub.PTATbias which increases proportionally with increasing absolute temperature. By supplying the base of the thermal shutdown transistor with a bias voltage V.sub.PTATbias which increases with increasing temperature rather than a bias voltage that remains constant or decreases with increasing temperature, the temperature at which the thermal shutdown transistor turns on is made more predictable and the thermal shutdown transistor is made to turn on more sharply at a desired thermal shutdown temperature. The bias voltage V.sub.PTATbias may be generated by driving a current which increases proportionally with increasing absolute temperature across a resistor. Current sources employing feedback control loops are disclosed for generating such a current. Startup current sources are disclosed for starting control loop operation.

Abstract: A digital value on a plurality of control input terminals of a PCMCIA power multiplexer integrated circuit determines which one if any of a plurality of power input terminals (for example, 12 volts, 5 volts, and 3 volts) is coupled through the integrated circuit to a power output terminal. A decoder which decodes the digital value prevents any two of the power input terminals from being coupled to the power output terminal at the same time. The decoder is programmable so that a single power multiplexer integrated circuit die layout can support a variety of PCMCIA controllers outputting different digital values. The integrated circuit has current limit, controlled power turn on times, and overtemperature protection. A signal indicative of a fault condition (for example, an overtemperature or a current limit condition) is output onto a fault output terminal of the integrated circuit.

Abstract: An improved output driver is disclosed having a pull-off diode-connected transistor and a resistor for keeping a pass transistor off when no load current is desired. An MOS transistor is coupled in parallel with the pull-off diode. As the input voltage increases beyond a threshold level, the diode is no longer able to pull-off the pass transistor's base due to increasing leakage currents in the pass transistor and is thus unable to turn off the pass transistor. The MOS transistor turns on at this threshold voltage and pulls-off the pass transistor's base hard enough to keep the pass transistor off. In one embodiment, the MOS transistor is incorporated into an unadjusted field region of the diode-connected transistor without any additional masking or processing steps. Further, since it is formed in the field region of the diode, the inclusion of the MOS transistor requires no additional surface area.

Abstract: A lateral DMOS transistor structure formed in N-type silicon is disclosed which incorporates a special N-type enhanced drift region. In one embodiment, a cellular transistor with a polysilicon gate mesh is formed over an N epitaxial layer with P body regions, P.sup.+ body contact regions, N.sup.+ source and drain regions, and N enhanced drift regions. The N enhanced drift regions are more highly doped than the epitaxial layer and extend between the drain regions and the gate. Metal strips are used to contact the rows of source and drain regions. The N enhanced drift regions serve to significantly reduce on-resistance without significantly reducing breakdown voltage.

Abstract: A cellular transistor structure is disclosed which incorporates a polysilicon gate mesh. In one embodiment, the silicon under the polysilicon is of an N-type while the exposed area not covered by the polysilicon is doped with a P dopant to form P-type source and drain regions. Metal strips are used to contact the rows of source and drain cells. By forming the openings in the polysilicon mesh to be in a diamond shape (i.e., having a long diagonal and a short diagonal), the source and drain metal strips, arranged in the direction of the short diagonals, can be made wider and shorter, thus reducing the on-resistance of the transistor without increasing the area of the transistor.

Abstract: To avoid forward biasing the diodes within an N-channel transistor, the body and source of the N-channel transistor are switchably connected via a high-voltage FET. The gates of the N-channel transistor and high-voltage transistor are connected together so that both transistors are on or off simultaneously. When both transistors are on, the high-voltage transistor shorts the body and source of the N-channel transistor. When both transistors are off, the body and source of the N-channel transistor are disconnected and a third transistor couples the body to a reference potential. The N-channel transistor and high voltage transistor share a common body in a semiconductor substrate. The source of the N-channel transistor provides an output terminal for the circuit. A number of these devices, each connected to a different supply voltage, can be connected to the same output terminal and selectively energized to form a voltage multiplexer.

Abstract: A transistor structure incorporates a polysilicon layer which is doped with N-type dopants and is used as an emitter ballast resistor in an array of NPN transistors. In one embodiment, the polysilicon layer is also used as a diffusion source to form N-type emitter regions within a deep and high resistivity P-well, which acts as a relatively high value base ballast resistor for the transistor. In another embodiment, a standard base is used, contributing little base ballast resistance. A buried collector region carries collector current. Preferably, the emitter regions are formed as oblong strips. P-type base contact regions, also generally formed as oblong strips, are formed in the surface of this P-well parallel to the emitter regions. The dimensions of the base contact regions may be varied in order to achieve a constant base-emitter voltage along the entire length of each emitter strip.

Abstract: A cellular transistor structure is disclosed which incorporates a polysilicon gate mesh. In one embodiment, the silicon under the polysilicon is of an N-type while the exposed area not covered by the polysilicon is doped with a P dopant to form P-type source and drain regions. Metal strips are used to contact the rows of source and drain cells. By forming the openings in the polysilicon mesh to be in a diamond shape (i.e., having a long diagonal and a short diagonal), the source and drain metal strips, arranged in the direction of the short diagonals, can be made wider and shorter, thus reducing the on-resistance of the transistor without increasing the area of the transistor.