Patents by Inventor James C. Pattison

James C. Pattison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140173536
    Abstract: A system, a computer program product, and a computer-implemented method are provided for automatically generating a LVS rule file, and/or for automatically generating a regression test data suite.
    Type: Application
    Filed: December 17, 2012
    Publication date: June 19, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Vladimir V. Shtraikh, James M. Hiatt, James C. Pattison
  • Patent number: 8751988
    Abstract: A system, a computer program product, and a computer-implemented method are provided for automatically generating a LVS rule file, and/or for automatically generating a regression test data suite.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: June 10, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vladimir V. Shtraikh, James M. Hiatt, James C. Pattison
  • Patent number: 7315054
    Abstract: In one embodiment, a method of controlling the across-chip line-width variation (ACLV) on a semiconductor integrated circuit includes forming an ACLV controlled region including a plurality of semiconductor devices each having a gate structure and arranging the plurality of semiconductor devices to have a substantially uniform spacing between each gate structure. The method also includes forming a decoupling capacitor region adjacent to the ACLV controlled region. The decoupling capacitor region may include a plurality of capacitor structures each having a conductive structure, such as a polysilicon electrode, for example.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: January 1, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jerry D. Moench, James C. Pattison
  • Patent number: 6916716
    Abstract: Various methods of fabricating halo regions are disclosed. In one aspect, a method of manufacturing is provided that includes forming a symmetric transistor and an asymmetric transistor on a substrate. A first mask is formed on the substrate with a first opening to enable implantation formation of first and second halo regions proximate first and second source/drain regions of the symmetric transistor. First and second halo regions of a first dosage are formed beneath the first gate by implanting off-axis through the first opening. A second mask is formed on the substrate with a second opening to enable implantation formation of a third halo region proximate a source region of the second asymmetric transistor while preventing formation of a halo region proximate a drain region of the asymmetric transistor. A third halo region of a second dosage greater than the first dosage is formed by implanting off-axis through the second opening.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: July 12, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Scott Goad, James C. Pattison, Edward Ehrichs