Patents by Inventor James C. Secora

James C. Secora has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock circuitry for a data communication system
    Patent number: 4276651
    Abstract: A data communication system for use in the control and monitoring of mobile stations, for example, in a bus monitoring system, from a central station over a communication channel carrying both data and voice information. Information is encoded into digital messages having a start code followed by one or more data blocks. The start code identifies the beginning of the data block that follows and enables synchronization of clock circuitry to the received data frequency. The data blocks have N digital words with M binary bits where one word is a parity word and N-1 words are data words. Each of the data words has a data portion and parity portion coded for correction of at least one error. Reliability is enhanced by a data detector which discriminates between data and noise or voice to provide an indication of the presence of data. In transmitting the digital messages, the bits of the N words in each data block are interleaved to provide protection against error bursts.
    Type: Grant
    Filed: January 29, 1979
    Date of Patent: June 30, 1981
    Assignee: Motorola, Inc.
    Inventors: Stephen M. Bench, William R. Dirkes, Manohar A. Juglekar, James C. Secora, Michael A. Stephen
  • Data communication system with random and burst error protection and correction
    Patent number: 4156867
    Abstract: A data communication system for use in the control and monitoring of mobile stations, for example, in a bus monitoring system, from a central station over a communication channel carrying both data and voice information. Information is encoded into digital messages having a start code followed by one or more data blocks. The start code identifies the beginning of the data block that follows and enables synchronization of clock circuitry to the received data frequency. The data blocks have N digital words with M binary bits where one word is a parity word and N-1 words are data words. Each of the data words has a data portion and parity portion coded for correction of at least one error. Reliability is enhanced by a data detector which discriminates between data and noise or voice to provide an indication of the presence of data. In transmitting the digital messages, the bits of the N words in each data block are interleaved to provide protection against error bursts.
    Type: Grant
    Filed: September 6, 1977
    Date of Patent: May 29, 1979
    Assignee: Motorola, Inc.
    Inventors: Stephen M. Bench, William R. Dirkes, Manohar A. Joglekar, James C. Secora, Michael A. Stepien