Abstract: Conventionally, current detection in load switches is implemented by monitoring the voltage across a small value sense resistor in series with the load switch, where the differential voltage across is applied to a comparator to generate a control signal corresponding to a light load condition, a normal load condition, or an over-load condition. Detecting the light load condition, however, can be difficult to determine using this arrangement due to the low differential voltage. Here, however, a integrated circuit (IC) is provided that employs an internal voltage supply and comparators to examine the load current to determine whether a light load condition is present, which does not suffer from the same problems.

Abstract: Conventionally, current detection in load switches is implemented by monitoring the voltage across a small value sense resistor in series with the load switch, where the differential voltage across is applied to a comparator to generate a control signal corresponding to a light load condition, a normal load condition, or an over-load condition. Detecting the light load condition, however, can be difficult to determine using this arrangement due to the low differential voltage. Here, however, a integrated circuit (IC) is provided that employs an internal voltage supply and comparators to examine the load current to determine whether a light load condition is present, which does not suffer from the same problems.

Abstract: The voltage configurable circuit includes: a first transistor 20 having a first end coupled to a first power supply node VCCA; a second transistor 21 having a first end coupled to a second power supply node VCCB and cross-coupled with the first transistor 20; input buffers having input buffer supply nodes coupled to a second end of the first transistor 20 and a second end of the second transistor 21; a first output port A-port coupled to a first one of the input buffers; and a second output port B-port coupled to a second one of the input buffers.

Abstract: A CMOS output driver with a DC feedback circuit architecture that changes the output impedance of the driving transistors as the output voltage transition progresses. The output voltage slew rate is then controlled by limiting the gate voltages (node of Ng and Pg) of the output driver transistors during the transition.

Abstract: A CMOS output driver with a DC feedback circuit architecture that changes the output impedance of the driving transistors as the output voltage transition progresses. The output voltage slew rate is then controlled by limiting the gate voltages (node of Ng and Pg) of the output driver transistors during the transition.

Abstract: The voltage configurable circuit includes: a first transistor 20 having a first end coupled to a first power supply node VCCA; a second transistor 21 having a first end coupled to a second power supply node VCCB and cross-coupled with the first transistor 20; input buffers having input buffer supply nodes coupled to a second end of the first transistor 20 and a second end of the second transistor 21; a first output port A-port coupled to a first one of the input buffers; and a second output port B-port coupled to a second one of the input buffers.

Abstract: The output edge control circuit includes: a high side transistor 27coupled to an output node 44; a first low side transistor 20 coupled to the output node 44; a second low side transistor 24 coupled in parallel with the first low side transistor 20; a coupling transistor 23 coupled between the output node 44 and a control node of the second low side transistor 24; a transmission gate 50 coupled between a control node of the first low side transistor 20 and a control node of the coupling transistor 23; and feedback circuitry 58 coupled between the output node 44 and the transmission gate 50 for controlling the transmission gate 50.

Abstract: A circuit and method for providing a bus switch that translates voltage from one level to a second, lower level. A FET bus switch transistor 310 is integrated on the same silicon chip 320 with one or more diodes 330 in series with Vcc, the power supply 340. A bias current source 350 is included to bias the diode. The diodes and current source are configured to provide additional voltage translation so that when a control input couples the input pin at the source of the FET bus switch to the output pin at the drain of the FET bus switch, the voltage at the output pin can be placed at a predetermined level. The bus switch thus acts as both a bus coupling device and a voltage translation device.

Abstract: An output driver circuit for use with low voltage level, high speed data transmission busses which require slew and skew control of the output voltage transitions. An open collector output transistor has a controlled slew rate for both the high to low and low to high output transitions. The slew rate control is provided by controlling the slew rate of the base voltage of the output transistor in response to an input transition. A slew rate control circuit coupled to the output transistor includes a current source powered by a high stability bias generator, one or more output feedback circuits, an output level compensation circuit, and a base discharge circuit. The current source controls the amount of current available at the base of the open collector output transistor. The feedback circuits are used to control the initial voltage at the base of the output transistor, and the slew rate for the rising voltage at the base of the output transistor.

Abstract: A complimentary output pair (10) having a P-channel transistor (12) and an N-channel transistor (14) prevents output voltage spikes due to rapid changes in current with respect to time at the V.sub.cc power supply and ground (32) nodes by using a "graded turn-on." Both the P-channel transistor (12) and the N-channel (14) utilize a serpentine polysilicon gate (16), (24), in order to sequentially turn on the sub-transistors in response to a changing input. Pull-up (36) and pull-down (40) transistors are used to turn the sub-transistors (21a-j, 29a-f) off simultaneously.