Abstract: A method of performing an infinite-impulse response digital filter includes switching address pointers between a first instance of the filter and a second instance of the filter; where the first and second instances represent the same filter. A first instance of the filter executes operations sequentially multiplying a current input data value, and first and second previous input data values, with corresponding ones of a first set of filter coefficients, using a multiplier; and a second instance of the filter executes operations sequentially multiplying first and second previous intermediate data values with corresponding ones of a second set of filter coefficients, using the multiplier. Switching between first and second instances of the filter occurs at each data input value or frame according to an alternating signal.

Abstract: An audio processor for two way communication includes a signal generator for producing test signals coupled to selected test points in the audio processor. An echo canceling circuit and a voice detection circuit within the audio processor provide data representing the response of the audio processing circuit to said test signals. The test signals include a single tone signal and a sweep frequency signal. Data from the test is used for adjusting the audio processor according to the results of the tests.

Abstract: A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus. Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with devices (e.g., peripheral devices) connected to the I/O bus.

Abstract: A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus (e.g., peripheral devices). Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. Further, to reduce stalling of a processor seeking access to the main memory via the host bus and the internal bus, the host bus is able to gain access to the main memory using the internal bus during times in which the internal bus is temporarily not needed by the data transfer between the main memory and the peripheral devices.

Abstract: An I/O holdoff mechanism is used to compensate for I/O device inputs being fed through a latency introducing bus. A system includes one or more I/O devices connected through a serial bus to a controller device. Each I/O device includes at least one request pin which is connected to a peripheral device. A serializer in the I/O device responds to a voltage transition occurring on any request pin of the I/O device by forwarding, in a packet over the serial bus, an indicator. The indicator indicates a current voltage on the request pin of the I/O device on which the voltage transition occurred. The controller device includes a deserializer and a bus controller. The deserializer receives the first packet and outputs a signal which indicates a current value for the voltage on the indicated request pin. The deserializer includes a busy output which indicates when the deserializer is busy and when the deserializer is idle.

Abstract: An improved carrel for subdividing the area of a table surface comprises at least one support assembly consisting of a plurality of separate support elements secured together by elastic clamping means and supporting vertical partitions between the surfaces of the support elements. The carrel is easily assembled and disassembled and can be used without marring or permanently altering the table.