Abstract: A multi-processor system is disclosed comprising a first processor, a first memory coupled to the first processor, a second processor, and a shared memory subsystem including a shared memory and a data transfer unit. The first processor is configured to build a data structure in the first memory and to send a direct memory access (DMA) transfer request to the data transfer unit of the shared memory subsystem, the DMA transfer request including an address of the data structure in the first memory. The data transfer unit is configured to retrieve the data structure from the first memory based on the DMA transfer request, to store the data structure in the shared memory, and to send a shared memory pointer to the second processor indicating an address of the data structure in the shared memory.

Abstract: A system is disclosed comprising a processor, a trace module, a second buffer, and a bridge. The trace module has a first buffer configured to receive trace data from the processor at a first clock frequency. The second buffer is configured to receive trace data from the first buffer at a second clock frequency. The bridge is configured to receive trace data from the second buffer and output the trace data received from the second buffer at a third clock frequency. The second clock frequency is greater than the first clock frequency and the third clock frequency.

Abstract: A system is disclosed comprising a processor, and a debug circuit. The debug circuit comprises a reset circuit configured to detect when the system is released from a reset, a debugger detection circuit configured to detect whether an external debugger is connected to the system at a time the reset circuit detects a release from the reset, and a halt circuit configured to halt operation of the processor when the debugger detection circuit detects the debugger at the time of release from the reset.

Abstract: An audio/video (A/V) system for storing A/V programs includes an interface configured to receive a transport stream structured in packets and representing a plurality of A/V programs. Each A/V program is represented by a plurality of packets and is identified by program identification data in each packet. A storage management system is connected to receive the transport stream from the interface and to detect the program identification data of each received packet. A buffer is coupled to the storage management system and has a plurality of separate buffer portions. Each buffer portion is in communication with the storage management system to receive data of packets having program identification data related to a single A/V program and to store the data of the packets separate from data of packets having program identification data related to different A/V programs. A storage medium is coupled to the storage management system and has a plurality of separate storage files for the A/V programs.