Abstract: A multistream data packet transfer apparatus and method receives data for at least one stream of multistream data from multiple fragments of memory, over a bus from a first processor. The first processor stores multistream data in the fragmented memory. An interface controller, such as any suitable logic and /or software, evaluates the received data to determine which received data is usable data for a second processor. A data packer removes unusable data and packs the usable data in fixed sized units to form a data packet for the second processor. The data packer packs data received from different fragments of memory as a single packet for use by a DSP requesting the information.

Abstract: A bus interface control system and method includes an on-demand bus master interface for independently requesting multistream data from host memory without interrupting processing of the host processor between independent requests for data packets. A plurality of digital signal processors share the host bus and utilize flexible data speed transfer depending upon demand of real time data that must be transferred from host memory. The master interface control system includes an packet by packet arbitor to facilitate maximum throughput of data on-demand by the plurality of processing unit.