Abstract: A multi-chip antenna diversity architecture includes a first receiver chip including a first tuner, and a first demodulator directly connected to the tuner. The first demodulator demodulates the first input signal received from the first tuner. A first power sequencer that controls the first receiver chip, and a first chip ID including a voltage source VSS that indicates the first receiver chip as a slave chip. A second receiver chip includes a second tuner, and a second demodulator directly connected to the second tuner. The second demodulator demodulates the second input signal received from the second tuner. A second diversity combiner directly connected to the second demodulator. A second chip ID includes a voltage source VDD that indicates the second receiver chip as a master chip. A Diversity State Machine (DSM) controls an operating state of the first receiver chip and the second receiver chip that are structurally identical.

Abstract: A multi-chip antenna diversity architecture and method includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first tuner that amplifies the first input signal, a crystal operatively connected to a first crystal oscillator circuit, and a first crystal oscillator clock buffer that receives a clock signal from the first crystal oscillator circuit. A first demodulator demodulates the input signal received from the first tuner. A second receiver chip receives a second input signal from a second antenna. The second receiver chip includes a second crystal oscillator circuit, a second crystal oscillator clock buffer, a second tuner, and a second demodulator that receives diversity data from the first demodulator. The first crystal oscillator clock buffer drives the clock signal to the second crystal oscillator clock buffer, the second tuner, and the second demodulator of the second receiver chip.

Abstract: A multi-chip antenna diversity architecture includes a first receiver chip including a first tuner, and a first demodulator directly connected to the tuner. The first demodulator demodulates the first input signal received from the first tuner. A first power sequencer that controls the first receiver chip, and a first chip ID including a voltage source VSS that indicates the first receiver chip as a slave chip. A second receiver chip includes a second tuner, and a second demodulator directly connected to the second tuner. The second demodulator demodulates the second input signal received from the second tuner. A second diversity combiner directly connected to the second demodulator. A second chip ID includes a voltage source VDD that indicates the second receiver chip as a master chip. A Diversity State Machine (DSM) controls an operating state of the first receiver chip and the second receiver chip that are structurally identical.

Abstract: A multi-chip antenna diversity architecture and method includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first tuner that amplifies the first input signal, a crystal operatively connected to a first crystal oscillator circuit, and a first crystal oscillator clock buffer that receives a clock signal from the first crystal oscillator circuit. A first demodulator demodulates the input signal received from the first tuner. A second receiver chip receives a second input signal from a second antenna. The second receiver chip includes a second crystal oscillator circuit, a second crystal oscillator clock buffer, a second tuner, and a second demodulator that receives diversity data from the first demodulator. The first crystal oscillator clock buffer drives the clock signal to the second crystal oscillator clock buffer, the second tuner, and the second demodulator of the second receiver chip.

Abstract: A multi-chip antenna diversity architecture includes a first receiver chip including a first tuner, and a first demodulator directly connected to the tuner. The first demodulator demodulates the first input signal received from the first tuner. A first power sequencer that controls the first receiver chip, and a first chip ID including a voltage source VSS that indicates the first receiver chip as a slave chip. A second receiver chip includes a second tuner, and a second demodulator directly connected to the second tuner. The second demodulator demodulates the second input signal received from the second tuner. A second diversity combiner directly connected to the second demodulator. A second chip ID includes a voltage source VDD that indicates the second receiver chip as a master chip. A Diversity State Machine (DSM) controls an operating state of the first receiver chip and the second receiver chip that are structurally identical.

Abstract: A multi-chip antenna diversity architecture and method includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first tuner that amplifies the first input signal, a crystal operatively connected to a first crystal oscillator circuit, and a first crystal oscillator clock buffer that receives a clock signal from the first crystal oscillator circuit. A first demodulator demodulates the input signal received from the first tuner. A second receiver chip receives a second input signal from a second antenna. The second receiver chip includes a second crystal oscillator circuit, a second crystal oscillator clock buffer, a second tuner, and a second demodulator that receives diversity data from the first demodulator. The first crystal oscillator clock buffer drives the clock signal to the second crystal oscillator clock buffer, the second tuner, and the second demodulator of the second receiver chip.

Abstract: A multi-chip antenna diversity architecture and method includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first tuner that amplifies the first input signal, a crystal operatively connected to a first crystal oscillator circuit, and a first crystal oscillator clock buffer that receives a clock signal from the first crystal oscillator circuit. A first demodulator demodulates the input signal received from the first tuner. A second receiver chip receives a second input signal from a second antenna. The second receiver chip includes a second crystal oscillator circuit, a second crystal oscillator clock buffer, a second tuner, and a second demodulator that receives diversity data from the first demodulator. The first crystal oscillator clock buffer drives the clock signal to the second crystal oscillator clock buffer, the second tuner, and the second demodulator of the second receiver chip.

Abstract: A multi-chip antenna diversity architecture includes a first receiver chip including a first tuner, and a first demodulator directly connected to the tuner. The first demodulator demodulates the first input signal received from the first tuner. A first power sequencer that controls the first receiver chip, and a first chip ID including a voltage source VSS that indicates the first receiver chip as a slave chip. A second receiver chip includes a second tuner, and a second demodulator directly connected to the second tuner. The second demodulator demodulates the second input signal received from the second tuner. A second diversity combiner directly connected to the second demodulator. A second chip ID includes a voltage source VDD that indicates the second receiver chip as a master chip. A Diversity State Machine (DSM) controls an operating state of the first receiver chip and the second receiver chip that are structurally identical.