Abstract: A new method of depositing PE-oxide or PE-TEOS. An HDP-oxide is provided over a pattern of polysilicon. An etch back is performed to the deposited HDP-oxide, a layer of plasma-enhanced SiN is deposited. This PE-SiN is etched back leaving SiN spacers on the sidewalls of the poly pattern, further leaving a deposition of HDP-oxide on the top surface of the poly pattern. The profile of the holes within the poly pattern in such that the final layer of PE-oxide or PE-TEOS is deposited without resulting in the formation of keyholes in this latter layer.

Abstract: A method using a single masking step for making double-cylinder stacked capacitors for DRAMs which increases capacitance while eliminating erosion of an underlying oxide insulating layer when the masking step is misaligned is described. A planar silicon oxide (SiO2) first insulating layer is formed over device areas, and a first silicon nitride (Si3N4) etch-stop layer is deposited, and openings are etched for capacitor node contacts. A first polysilicon layer is deposited to a thickness sufficient to fill the openings and to form an essentially planar surface. A second insulating layer is deposited and patterned to form portions with vertical sidewalls over the node contacts. A conformal second Si3N4 layer is deposited and etched back to form spacers on the vertical sidewalls, and the first polysilicon layer is etched to the first Si3N4 layer. The second insulating layer is selectively removed using HF acid while the first polysilicon and first Si3N4 layers prevent etching of the underlying first SiO2 layer.

Abstract: A method for fabricating a microelectronic layer. There is first provided a substrate. There is then formed over the substrate a target layer. There is then formed upon the target layer a patterned photoresist layer which defines a first aperture, where the first aperture has a first aperture width which exposes a first portion of the target layer. There is then reflowed thermally the patterned photoresist layer to form a reflowed patterned photoresist layer which defines a substantially straight sided second aperture. The second aperture has a second aperture width less than the first aperture width, and the second aperture thus exposes a second portion of the blanket target layer of areal dimension less than the first portion of the blanket target layer. Finally, there is then fabricated the target layer to form a fabricated target layer while employing the reflowed patterned photoresist layer as a mask layer.

Abstract: A method is disclosed for forming self-aligned, borderless contact and vias together and simultaneously with relaxed photolithographic alignment tolerances using a modified dual damascene process having two etch-stop layers. A first etch-stop layer is formed over a first dielectric layer. A second dielectric layer and a second etch-stop layer are next formed sequentially over the first etch-stop layer. Contact/via hole pattern is etched into the first etch-stop layer using a first photoresist layer. A second photoresist layer, patterned with metal line trench pattern, is formed over the contact/via patterned first etch-stop layer. The contact/via hole openings are etched into the first dielectric layer until the second etch-stop layer is reached. Then, both the first and second etch-stop layers are etched through the openings.

Abstract: A process for fabricating a crown shaped, capacitor structure, in a SAC opening, featuring a silicon nitride spacer, located on the walls of a bottom portion of the SAC opening, has been developed. The process features forming a SAC opening in a thick silicon oxide layer, then repairing, or filling, seams or voids, that may be present in the thick silicon oxide layer, at the perimeter of the SAC opening, via formation of a silicon nitride spacer on the sides of the SAC opening. Subsequent processing features: the isotropic removal of a top portion of the silicon nitride spacer; the formation of a polysilicon storage node structure, in the SAC opening; and the recessing of a top portion of the thick silicon oxide layer, resulting in exposure of additional polysilicon storage node, surface area.

Abstract: A method for making a planar interlevel dielectric (ILD) layer, having improved thickness uniforming across the substrate surface, over a patterned electrically conducting layer is achieved. The method involves forming electrically conducting lines on which is deposited a conformal first insulating layer that is uniformly thick across the substrate. An etch-stop composed of Si3N4 is deposited and a second insulating layer, composed of SiO2 or a low-dielectric-constant insulator, is deposited. The second insulating layer is then partially chemically/mechanically polished back to within a few thousand Angstroms of the etch-stop layer. The remaining second insulating layer is then plasma etched back selectively to the etch-stop layer to form a planar surface having a uniformly thick first insulating layer over the electrically conducting lines. The contact openings or via holes can now etched to a uniform depth in the etch-stop layer and the first insulating layer across the substrate.

Abstract: A new method of maintaining good control of the dielectric thickness over a top capacitor plate during planarization by CMP by introducing a CMP stop layer under the topmost dielectric layer is described. Semiconductor device structures, including a node contact region, are provided in and on a semiconductor substrate. A bottom plate electrode is formed contacting the node contact region through an opening in a first insulating layer. A capacitor dielectric layer is deposited overlying the bottom plate electrode. A second conducting layer is deposited overlying the capacitor dielectric to form a top plate electrode of the capacitor. A second insulating layer is deposited overlying the second conducting layer. A silicon nitride polish stop layer is deposited overlying the second insulating layer. The polish stop layer, second insulating layer, second conducting layer, and capacitor dielectric layer are patterned to form the DRAM integrated circuit device.

Abstract: A process for forming a crown shaped, polysilicon storage node structure, for a DRAM capacitor structure, has been developed. The process features the deposition of a polysilicon layer, on the top surface of a thick insulator layer, as well as on all surfaces of an opening, in the thick insulator layer. Removal of the regions of polysilicon, residing on the top surface of the thick insulator layer, results in a crown shaped, polysilicon storage node structure, in the opening, in the thick insulator layer. The crown shaped, polysilicon storage node structure, was protected from the polysilicon removal procedure, by a photoresist plug, formed overlying the polysilicon layer, in the opening, in the thick insulator layer. The photoresist plug was formed via photoresist application, exposure, and the development of exposed photoresist regions.

Abstract: A process for forming a crown shaped storage node structure, for a DRAM capacitor structure, has been developed. The process features the patterning of a top portion, of a storage node contact plug structure, after patterning of the crown shaped storage node structure, and after removal of a silicon oxide layer, used for the definition of the crown shaped storage node structure. The sequence of patterning steps allows mis-alignment between the crown shaped storage node structure, and the underlying storage node contact hole, to occur without vulnerability to insulator layers used to passivate the transfer gate transistors, of the DRAM cell. This process also features the use of a photoresist plug, used to protect a bottom shape, of the crown shaped storage node structure during the crown shaped storage node, and the storage node contact plug structure, patterning procedures.