Patents by Inventor James Coke
James Coke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140189311Abstract: An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data elements is accessed. A second packed data operand having at least two data elements is accessed. One of the data elements in the first packed data operand is shuffled into a lower destination field of a destination register, and one of the data elements in the second packed data operand is shuffled into an upper destination field of the destination register.Type: ApplicationFiled: December 31, 2012Publication date: July 3, 2014Inventors: Patrice Roussel, Srinivas Chennupaty, Michael Cranford, Mohammad Abdallah, James Coke, Katherine Kong
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Patent number: 7467286Abstract: A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands that include data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set specify operations to be performed on all of the data elements. In contrast, each of the instructions in the second set specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either the first or second set of instructions.Type: GrantFiled: May 9, 2005Date of Patent: December 16, 2008Assignee: Intel CorporationInventors: Mohammad Abdallah, James Coke, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar
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Patent number: 7430578Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed byte data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed byte data and a second packed byte data. The processor performs operations on data elements in said first packed byte data and said second packed byte data to generate a third packed data in response to receiving an instruction. A plurality of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed byte data.Type: GrantFiled: June 30, 2003Date of Patent: September 30, 2008Assignee: Intel CorporationInventors: Eric Debes, William W. Macy, Jonathan J. Tyler, James Coke, Frank Binns, Scott Rodgers, Peter Ruscito, Bret Toll, Vesselin Naydenov, Masood Tahir, David Jackson
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Patent number: 6970994Abstract: A method and apparatus for executing partial-width packed data instructions are discussed. The processor may include a plurality of registers, a register renaming unit, a decoder, and a partial-width execution unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. The first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, the second set of instructions specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either of the first or the second set of instructions.Type: GrantFiled: May 8, 2001Date of Patent: November 29, 2005Assignee: Intel CorporationInventors: Mohammad Abdallah, James Coke, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar
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Publication number: 20050216706Abstract: A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands that include data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set specify operations to be performed on all of the data elements. In contrast, each of the instructions in the second set specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either the first or second set of instructions.Type: ApplicationFiled: May 9, 2005Publication date: September 29, 2005Inventors: Mohammad Abdallah, James Coke, Vladimir Pentkovski, Patrice Roussel, Shreekant Thakkar
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Publication number: 20040073589Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed byte data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed byte data and a second packed byte data. The processor performs operations on data elements in said first packed byte data and said second packed byte data to generate a third packed data in response to receiving an instruction. A plurality of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed byte data.Type: ApplicationFiled: June 30, 2003Publication date: April 15, 2004Inventors: Eric Debes, William W. Macy, Jonathan J. Tyler, James Coke, Frank Binns, Scott Rodgers, Peter Ruscito, Bret Toll, Vesselin Naydenov, Masood Tahir, David Jackson
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Publication number: 20020010847Abstract: A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, each of the instructions in the second set of instructions specify operations to be performed on only a subset of the data element stored in the one or more specified registers.Type: ApplicationFiled: May 8, 2001Publication date: January 24, 2002Inventors: Mohammad Abdallah, James Coke, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar
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Patent number: 6192467Abstract: A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, each of the instructions in the second set of instructions specify operations to be performed on only a subset of the data element stored in the one or more specified registers.Type: GrantFiled: March 31, 1998Date of Patent: February 20, 2001Assignee: Intel CorporationInventors: Mohammad A. Abdallah, Vladimir Pentkovski, James Coke
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Patent number: 6122725Abstract: A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, and a decoder coupled to the register renaming unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions (e.g., a set of full-width packed data instructions and a set of partial-width packed data instructions) that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers.Type: GrantFiled: March 31, 1998Date of Patent: September 19, 2000Assignee: Intel CorporationInventors: Patrice Roussel, Ticky Thakkar, Mohammad A. Abdallah, Vladimir Pentkovski, James Coke
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Patent number: 6026455Abstract: A bridge circuit adapted to be associated with a PCI and a secondary bus circuits which bridge circuit includes circuitry for storing an indication that a particular PCI bus master has attempted an access of the secondary bus and has been forced to retry that access, circuitry for masking any retry until the bus is again available, and circuitry for providing an interval during which a retrying PCI bus master is guaranteed access to the secondary bus in favor of a bus master on the secondary bus after the bus is relinquished so that a sequence of retry operations causing a loss of bandwidth on the PCI bus is not generated.Type: GrantFiled: February 24, 1994Date of Patent: February 15, 2000Assignee: Intel CorporationInventors: Nilesh Shah, James Coke, Jasmin Ajanovic, Dahmane Dahmani, Rajeev Prasad
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Patent number: 5455915Abstract: A bridge circuit adapted to be associated with a first and a second bus circuit which includes a first unidirectional path including a buffer for storing read data or addresses, a second unidirectional path including a buffer for storing write data or addresses, a third direct unidirectional path, an input circuit for multiplexing data or addresses from either of the first or second bus circuits, an output circuit for transferring data from any of the three unidirectional paths to either the first or the second bus circuit, and sources of signals for controlling the particular unidirectional path taken depending on the transfer operation being accomplished.Type: GrantFiled: December 16, 1993Date of Patent: October 3, 1995Assignee: Intel CorporationInventor: James Coke
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Patent number: RE45458Abstract: An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data elements is accessed. A second packed data operand having at least two data elements is accessed. One of the data elements in the first packed data operand is shuffled into a lower destination field of a destination register, and one of the data elements in the second packed data operand is shuffled into an upper destination field of the destination register.Type: GrantFiled: March 21, 2002Date of Patent: April 7, 2015Assignee: Intel CorporationInventors: Patrice Roussel, Srinivas Chennupaty, Micheal D. Cranford, Mohammed A. Abdallah, James Coke, Katherine Kong