Abstract: Disclosed herein are techniques for reducing standby power consumption due to leakage currents in memory circuits.

Abstract: Disclosed herein are techniques for reducing standby power consumption due to leakage currents in memory array circuits.

Abstract: An input buffer circuit includes an input buffer. The input buffer has an input adapted to be coupled to an address bus and a power down input. The input buffer circuit further includes power down circuitry adapted to be coupled to an address bus strobe and coupled to the power down input. When the address bus is detected to be idle by the power down circuitry, a power down signal is sent to the power down input. This powers down the input buffer.

Abstract: A synchronous interface to a self-timed memory array includes one or more address bus inputs and a first latch stage that includes one or more latches. Each of the latches of the first latch stage includes an input coupled to one of the address bus inputs and a first output. The synchronous interface further includes a second latch stage that includes a plurality of latches. Each of the latches of the second latch stage includes an input coupled to one of the first outputs of the first latch stage and a second output coupled to the memory array.

Abstract: A circuit and method in a computer system for generating a power-up reset pulse is disclosed. A specially designed flip-flop and a voltage shifter create a signal that ramps-up with a rising voltage from a newly activated power supply until a desired voltage level is reached. The signal is then deasserted and, in one embodiment, the circuit is reset so that another reset signal can be generated should power be removed and then reapplied in a short period of time. This circuit is configured so that no DC current paths from power to ground exist within the circuit once the reset pulse generation is complete.