Patents by Inventor James Cotronakis

James Cotronakis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11329013
    Abstract: Interconnected substrate arrays, microelectronic packages, and methods for fabricating microelectronic packages for fabricating microelectronic packages utilizing interconnected substrate arrays containing integrated electrostatic discharge (ESD) protection grids are provided. In an embodiment, the method includes obtaining an interconnected substrate array having an integrated ESD protection grid. The ESD protection grid includes, in turn, ESD grid lines at least partially formed in singulation streets of an interconnected substrate array and electrically coupling die attachment regions of the substrate array to one or more peripheral machine ground contacts. Array-level fabrication steps are performed to produce an interconnected package array utilizing the interconnected substrate array, while electrically coupling the die attachment regions to electrical ground through the ESD protection grid during at least one of the array-level fabrication steps.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: May 10, 2022
    Assignee: NXP USA, Inc.
    Inventors: James Cotronakis, Jose Luis Suarez, Eduard Jan Pabst
  • Publication number: 20210375797
    Abstract: Interconnected substrate arrays, microelectronic packages, and methods for fabricating microelectronic packages for fabricating microelectronic packages utilizing interconnected substrate arrays containing integrated electrostatic discharge (ESD) protection grids are provided. In an embodiment, the method includes obtaining an interconnected substrate array having an integrated ESD protection grid. The ESD protection grid includes, in turn, ESD grid lines at least partially formed in singulation streets of an interconnected substrate array and electrically coupling die attachment regions of the substrate array to one or more peripheral machine ground contacts. Array-level fabrication steps are performed to produce an interconnected package array utilizing the interconnected substrate array, while electrically coupling the die attachment regions to electrical ground through the ESD protection grid during at least one of the array-level fabrication steps.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 2, 2021
    Inventors: James Cotronakis, Jose Luis Suarez, Eduard Jan Pabst