Patents by Inventor James Culp

James Culp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210133293
    Abstract: One illustrative system includes a processor and memory storing instructions that, when executed by the processor, cause the system to receive a device layout including a curvilinear feature, define a plurality of vertices for the curvilinear feature, determine a radius of curvature between a selected vertex in the plurality of vertices and a neighboring vertex in the plurality of vertices, and identify a design rule violation for the curvilinear feature responsive to the radius of curvature being less than a predetermined threshold.
    Type: Application
    Filed: October 31, 2019
    Publication date: May 6, 2021
    Inventors: Ahmed Hassan, James Culp
  • Patent number: 10997355
    Abstract: One illustrative system includes a processor and memory storing instructions that, when executed by the processor, cause the system to receive a device layout including a curvilinear feature, define a plurality of vertices for the curvilinear feature, determine a radius of curvature between a selected vertex in the plurality of vertices and a neighboring vertex in the plurality of vertices, and identify a design rule violation for the curvilinear feature responsive to the radius of curvature being less than a predetermined threshold.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: May 4, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Ahmed Hassan, James Culp
  • Patent number: 9075106
    Abstract: An emission map of a circuit to be tested for alterations is obtained by measuring the physical circuit to be tested. An emission map of a reference circuit is obtained by measuring a physical reference circuit or by simulating the emissions expected from the reference circuit. The emission map of the circuit to be tested is compared with the emission map of the reference circuit, to determine presence of alterations in the circuit to be tested, as compared to the reference circuit.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: July 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, James Culp, David F. Heidel, Dirk Pfeiffer, Anthony D. Polson, Peilin Song, Franco Stellari, Robert L. Wisnieff
  • Publication number: 20110026806
    Abstract: An emission map of a circuit to be tested for alterations is obtained by measuring the physical circuit to be tested. An emission map of a reference circuit is obtained by measuring a physical reference circuit or by simulating the emissions expected from the reference circuit. The emission map of the circuit to be tested is compared with the emission map of the reference circuit, to determine presence of alterations in the circuit to be tested, as compared to the reference circuit.
    Type: Application
    Filed: July 30, 2009
    Publication date: February 3, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kerry Bernstein, James Culp, David F. Heidel, Dirk Pfeiffer, Anthony D. Polson, Peilin Song, Franco Stellari, Robert L. Wisnieff
  • Publication number: 20070220476
    Abstract: A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.
    Type: Application
    Filed: January 10, 2006
    Publication date: September 20, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Maharaj Mukherjee, James Culp, Lars Liebmann, Scott Mansfield
  • Publication number: 20070212863
    Abstract: A method of forming a planar CMOS transistor divides the step of forming the gate layer into a first step of patterning a resist layer with a first portion of the gate layer pattern and then etching the polysilicon with the pattern of the gates. A second step patterns a second resist layer with the image of the gate pads and local interconnect and then etching the polysilicon with the pattern of the gate pads and local interconnect, thereby reducing the number of diffraction and other cross-talk from different exposed areas.
    Type: Application
    Filed: March 7, 2006
    Publication date: September 13, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Brunner, James Culp, Lars Liebmann
  • Publication number: 20070164113
    Abstract: Mass-customized parts are identified by encoding part identification information into a multi-dimensional bar code, wherein mass-customization machinery, such as stereolithography apparatus, is used to make the parts with the multi-dimensional bar code embedded therein.
    Type: Application
    Filed: March 16, 2007
    Publication date: July 19, 2007
    Inventors: James Culp, Kwan Ho, Shiva Sambu, Srinivas Kaza, Craig Farren, Samuel Kass, Sergey Nikolsky
  • Publication number: 20070106968
    Abstract: An iterative timing analysis is analytically performed before a chip is fabricated, based on a methodology using optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time sensitive devices. The additional mask is used as a selective trim to form shortened gate lengths or wider metal lines for the selected, predetermined transistors, affecting the threshold voltages and the RC time constants of the selected devices. Marker shapes identify a predetermined subgroup of circuitry that constitutes the devices in the critical timing path. The analysis methodology is repeated as often as needed to improve the timing of the circuit with shortened designed gate lengths and modified RC timing constants until manufacturing limits are reached. A mask is made for the selected critical devices using OPC techniques.
    Type: Application
    Filed: November 8, 2005
    Publication date: May 10, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James Culp, Lars Liebmann, Rajeev Malik, K. Paul Muller, Shreesh Narasimha, Stephen Runyon, Patrick Williams
  • Publication number: 20060270268
    Abstract: A design verification method, including (a) providing in a design a design electrically conducting line and a design contact region being in direct physical contact with the design electrically conducting line; (b) modeling a simulated electrically conducting line of the design electrically conducting line; (c) simulating a possible contact region of the design contact region, wherein the design contact region and the possible contact region are not identical; and (d) determining that the design electrically conducting line and the design contact region are potentially defective if an interfacing surface area of the simulated electrically conducting line and the possible contact region is less than a pre-specified value.
    Type: Application
    Filed: May 26, 2005
    Publication date: November 30, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James Bruce, James Culp, John Nickel, Jacek Smolinski
  • Publication number: 20060102725
    Abstract: Systems and methods are disclosed for identifying a mass-customized part by encoding a part identification into a multi-dimensional bar code; and using a stereolithography apparatus (SLA) to make the part with multi-dimensional bar code embedded therein.
    Type: Application
    Filed: October 18, 2005
    Publication date: May 18, 2006
    Inventors: James Culp, Kwan Ho, Shiva Sambu, Srinivas Kaza, Graig Farren, Samuel Kass, Sergey Nikolsky
  • Publication number: 20060036977
    Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
    Type: Application
    Filed: August 12, 2004
    Publication date: February 16, 2006
    Inventors: John Cohn, James Culp, Ulrich Finkler, Fook-Luen Heng, Mark Lavin, Jin Lee, Lars Liebmann, Gregory Northrop, Nakgeuon Seong, Rama Singh, Leon Stok, Pieter Woltgens
  • Publication number: 20060029515
    Abstract: Apparatus and methods for pumping and oxygenating blood are provided that include a gas removal system. An integrated blood processing unit is provided in which a gas removal/blood filter, pump and blood oxygenation element are mounted within a common housing. The gas removal system includes a sensor mounted on the housing to sense the presence of gas, and a valve is operably coupled to the sensor to evacuate gas from the system when the sensor detects an accumulation of gas.
    Type: Application
    Filed: September 26, 2005
    Publication date: February 9, 2006
    Applicant: Cardiovention, Inc.
    Inventors: Steven Stringer, Kevin Hultquist, Mehrdad Farhangnia, Ben Brian, Fred Linker, James Culp, Jean-Pierre Dueri, Thomas Afzal
  • Publication number: 20050261571
    Abstract: System and method for simultaneously tracking a position of a medical device and ablating a tissue within a body. The system includes a power supply, a navigation device, and a control circuit. The power supply generates a current that is suitable for ablating tissue, such as heart tissue. The navigation device establishes a three-dimensional reference coordinate system and identifies a location of an energy delivery device in relation to the established coordinate system. The control circuit switches or alternates between activating the power supply and acquiring ultrasound data that identifies the location of the medical device within the established coordinate system.
    Type: Application
    Filed: May 21, 2004
    Publication date: November 24, 2005
    Inventors: Nathaniel Willis, James Culp, Vincent Sullivan
  • Publication number: 20050150709
    Abstract: A dual-sectioned automotive propeller shaft features a weakened area in a first section. Under an axial load, the first section buckles transversely to a longitudinal axis of the shaft to absorb substantially all of the energy exerted against the shaft. A second section of the shaft is thereby isolated from consequences of the axial load enabling its placement and proximity to other components mounted to the undercarriage of the vehicle.
    Type: Application
    Filed: January 9, 2004
    Publication date: July 14, 2005
    Inventors: Nicolaos Tapazoglou, Hai Gu, Gerald Burke, Troy Cornell, James Culp, Mark Kirschmann, Douglas Nieset
  • Publication number: 20050117795
    Abstract: A mask inspection method and system. Provided is a mask fabrication database describing geometrical shapes S to be printed as part of a mask pattern on a reticle to fabricate a mask through use of a mask fabrication tooling. The shapes S appear on the mask as shapes S? upon being printed. At least one of the shapes S? may be geometrically distorted relative to a corresponding at least one of the shapes S due to a lack of precision in the mask fabrication tooling. Also provided is a mask inspection database to be used for inspecting the mask after the mask has been fabricated by the mask fabrication tooling. The mask inspection database describes shapes S? approximating the shapes S?. A geometric distortion between the shapes S? and S? is less than a corresponding geometric distortion between the shapes S? and S.
    Type: Application
    Filed: December 2, 2003
    Publication date: June 2, 2005
    Applicant: International Business Machines Corporation
    Inventors: Karen Badger, James Culp, Azalia Krasnoperova
  • Patent number: 6713791
    Abstract: A T-RAM array having a planar cell structure is presented. The T-RAM array includes n-MOS and p-MOS support devices which are fabricated by sharing process implant steps with T-RAM cells of the T-RAM array. A method is also presented for fabricating the T-RAM array having the planar cell structure. The method entails simultaneously fabricating a first portion of a T-RAM cell and the n-MOS support device; simultaneously fabricating a second portion of the T-RAM cell and the p-MOS support device; and finishing the fabrication of the T-RAM cell by interconnecting the T-RAM cell with the p-MOS and n-MOS support devices. The first portion of the T-RAM cell is a transfer gate and the second portion of the T-RAM cell is a gated-lateral thyristor storage element. Accordingly, process steps in fabricating the T-RAM cells are shared with process steps in fabricating the n-MOS and p-MOS support devices. The n-MOS and p-MOS support devices refer to sense amplifiers, wordline drivers, column and row decoders, etc.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: March 30, 2004
    Assignee: IBM Corporation
    Inventors: Louis L. Hsu, Rajiv V. Joshi, Fariborz Assaderaghi, Dan Moy, Werner Rausch, James Culp
  • Publication number: 20020100918
    Abstract: A T-RAM array having a planar cell structure is presented. The T-RAM array includes n-MOS and p-MOS support devices which are fabricated by sharing process implant steps with T-RAM cells of the T-RAM array. A method is also presented for fabricating the T-RAM array having the planar cell structure. The method entails simultaneously fabricating a first portion of a T-RAM cell and the n-MOS support device; simultaneously fabricating a second portion of the T-RAM cell and the p-MOS support device; and finishing the fabrication of the T-RAM cell by interconnecting the T-RAM cell with the p-MOS and n-MOS support devices. The first portion of the T-RAM cell is a transfer gate and the second portion of the T-RAM cell is a gated-lateral thyristor storage element. Accordingly, process steps in fabricating the T-RAM cells are shared with process steps in fabricating the n-MOS and p-MOS support devices. The n-MOS and p-MOS support devices refer to sense amplifiers, wordline drivers, column and row decoders, etc.
    Type: Application
    Filed: January 26, 2001
    Publication date: August 1, 2002
    Inventors: Louis L. Hsu, Rajiv V. Joshi, Fariborz Assaderaghi, Dan Moy, Werner Rausch, James Culp