Patents by Inventor James D. Burrell

James D. Burrell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9184144
    Abstract: Pillars having a directed compliance geometry are arranged to couple a semiconductor die to a substrate. The direction of maximum compliance of each pillar may be aligned with the direction of maximum stress caused by unequal thermal expansion and contraction of the semiconductor die and substrate. Pillars may be designed and constructed with various shapes having particular compliance characteristics and particular directions of maximum compliance. The shape and orientation of the pillars may be selected as a function of their location on a die to accommodate the direction and magnitude of stress at their location. A method includes fabricating pillars with particular shapes by patterning to increase surface of materials upon which the pillar is plated or deposited.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: November 10, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Zhongping Bao, James D. Burrell, Shiqun Gu
  • Patent number: 8937384
    Abstract: At least one feature pertains to an apparatus having passive thermal management that includes an integrated circuit die, a heat spreader thermally coupled to the integrated circuit die, a phase change material (PCM) thermally coupled to the heat spreader, and a molding compound that encases the heat spreader and the PCM. In one example, the heat spreader may include a plurality of fins, and at least a portion of the PCM is interposed between the plurality of fins. Another feature pertains to an apparatus that includes an integrated circuit die, and a molding compound having a phase change material intermixed therein. The resulting molding compound completely encases the die.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: January 20, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Zhongping Bao, James D. Burrell, Liang Cheng
  • Patent number: 8601428
    Abstract: Various embodiments of methods and systems for heuristic determination and thermal analysis of component placement on a printed circuit board (“PCB”) for use in a portable computing device (“PCD”) are disclosed. It is an advantage of embodiments that thermal energy generating components, such as processors, may be heuristically selected and arranged on a selected PCB according to varying layouts and combinations and then evaluated for thermal dissipation efficiency under an assortment of use case scenarios. In this way, users of the system and method may quickly narrow down commercially feasible component layouts, identify the most efficient layouts and then heuristically modify the layouts to develop an optimal arrangement.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: December 3, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: James D. Burrell, Zhongping Bao, Liang Cheng, Damion B. Gastelum, Gary D. Good, Mohammed A. Tantoush, Jon J. Anderson
  • Publication number: 20130285233
    Abstract: At least one feature pertains to an apparatus having passive thermal management that includes an integrated circuit die, a heat spreader thermally coupled to the integrated circuit die, a phase change material (PCM) thermally coupled to the heat spreader, and a molding compound that encases the heat spreader and the PCM. In one example, the heat spreader may include a plurality of fins, and at least a portion of the PCM is interposed between the plurality of fins. Another feature pertains to an apparatus that includes an integrated circuit die, and a molding compound having a phase change material intermixed therein. The resulting molding compound completely encases the die.
    Type: Application
    Filed: April 25, 2012
    Publication date: October 31, 2013
    Applicant: QUALCOMM Incorporated
    Inventors: Zhongping Bao, James D. Burrell
  • Publication number: 20130167103
    Abstract: Various embodiments of methods and systems for heuristic determination and thermal analysis of component placement on a printed circuit board (“PCB”) for use in a portable computing device (“PCD”) are disclosed. It is an advantage of embodiments that thermal energy generating components, such as processors, may be heuristically selected and arranged on a selected PCB according to varying layouts and combinations and then evaluated for thermal dissipation efficiency under an assortment of use case scenarios. In this way, users of the system and method may quickly narrow down commercially feasible component layouts, identify the most efficient layouts and then heuristically modify the layouts to develop an optimal arrangement.
    Type: Application
    Filed: June 29, 2012
    Publication date: June 27, 2013
    Applicant: QUALCOMM INCORPORATED
    Inventors: James D. Burrell, Zhongping Bao, Liang Cheng, Damion B. Gastelum, Gary D. Good, Mohammed A. Tantoush, Jon J. Anderson
  • Publication number: 20130090888
    Abstract: Various embodiments of methods and systems for leveraging a user proximity measurement to determine thermal management policies in a portable computing device (“PCD”) are disclosed. By leveraging the proximity measurement to set temperature thresholds, the quality of service (“QoS”) provided by the PCD can be optimized when touch temperature of the PCD is not a significant factor for user experience. One such method involves monitoring a proximity signal to determine relative physical proximity of the PCD to a user. Based on the user proximity, a temperature threshold associated with a temperature sensor may be set and compared with an actual temperature measurement received from the temperature sensor. Based on the comparison, thermal management policies in the PCD can be evaluated. For instance, if the temperature threshold is higher than the actual measurement, PCD components may be allowed to increase power consumption, even though PCD temperature may rise, thereby optimizing QoS.
    Type: Application
    Filed: November 4, 2011
    Publication date: April 11, 2013
    Applicant: QUALCOMM Incorporated
    Inventors: Jon J. Anderson, Gary D. Good, James D. Burrell
  • Publication number: 20130020711
    Abstract: Pillars having a directed compliance geometry are arranged to couple a semiconductor die to a substrate. The direction of maximum compliance of each pillar may be aligned with the direction of maximum stress caused by unequal thermal expansion and contraction of the semiconductor die and substrate. Pillars may be designed and constructed with various shapes having particular compliance characteristics and particular directions of maximum compliance. The shape and orientation of the pillars may be selected as a function of their location on a die to accommodate the direction and magnitude of stress at their location. A method includes fabricating pillars with particular shapes by patterning to increase surface of materials upon which the pillar is plated or deposited.
    Type: Application
    Filed: July 21, 2011
    Publication date: January 24, 2013
    Applicant: QUALCOMM INCORPORATED
    Inventors: Zhongping Bao, James D. Burrell, Shiqun Gu