Patents by Inventor James D. Chlipala

James D. Chlipala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7174532
    Abstract: The present invention provides a method for manufacturing a semiconductor device, comprising: determining an isolation structure stress effect of a first semiconductor device, determining an optical proximity effect of a second semiconductor device, selecting a modeling design parameter such that the isolation structure stress effect is offset against the optical proximity effect on a fabrication model, and using the selected design parameter to construct a third semiconductor device.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: February 6, 2007
    Assignee: Agere Systems, Inc.
    Inventors: James D. Chlipala, Shahriar Moinian
  • Patent number: 6700944
    Abstract: A method and apparatus for detecting the phase difference between an input data signal and a local clock signal is provided. An input data signal is frequency divided and then fed through a series connection of a pair of data latches. Signals provided at the input and outputs of the pair of the data latches are exclusively-ORed to provide a variable width pulse signal and a reference pulse signal that may be used in a phase-locked loop to align the local clock with the input data signal in a predetermined phase relationship. A re-timed data signal is provided by inputting the input data signal to a data latch clocked with an inverted phase-aligned clock signal.
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: March 2, 2004
    Assignee: Agere Systems Inc.
    Inventors: James D. Chlipala, John M. Khoury, Kadaba R. Lakshmikumar, Peter C. Metz
  • Patent number: 5025300
    Abstract: An integrated circuit includes a conductive fusible link (14) that may be blown by laser energy. The dielectric material (15) covering the fuse is etched away to expose the fuse. A protective dielectric layer (30) is formed on the fuse to a controlled thickness less than that of the interlevel dielectric. The resulting structure prevents shorts between conductors that might otherwise occur due to debris from the fuse-blowing operation, and provides protection to the integrated circuit. In addition, the fuse blowing operation is more consistent from fuse to fuse.
    Type: Grant
    Filed: July 25, 1990
    Date of Patent: June 18, 1991
    Assignee: AT&T Bell Laboratories
    Inventors: James N. Billig, James D. Chlipala, Kuo H. Lee, William J. Nagy
  • Patent number: 5021362
    Abstract: A single beam of radiation is split and part of the beam is directed to conductive links, e.g. runners on a substrate. Analysis of the incident beam and the beam reflected from the substrate permits a determination of when the link is blown and rendered non-conductive and when significant substrate involvement occurs.
    Type: Grant
    Filed: December 29, 1989
    Date of Patent: June 4, 1991
    Assignee: AT&T Bell Laboratories
    Inventor: James D. Chlipala