Patents by Inventor James D. Guilford

James D. Guilford has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180095750
    Abstract: Methods and apparatuses relating to offload operations are described. In one embodiment, a hardware processor includes a core to execute a thread and offload an operation; and a first and second hardware accelerator to execute the operation, wherein the first and second hardware accelerator are coupled to shared buffers to store output data from the first hardware accelerator and provide the output data as input data to the second hardware accelerator, an input buffer descriptor array of the second hardware accelerator with an entry for each respective shared buffer, an input buffer response descriptor array of the second hardware accelerator with a corresponding response entry for each respective shared buffer, an output buffer descriptor array of the first hardware accelerator with an entry for each respective shared buffer, and an output buffer response descriptor array of the first hardware accelerator with a corresponding response entry for each respective shared buffer.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: TRACY GARRETT DRYSDALE, VINODH GOPAL, JAMES D. GUILFORD
  • Patent number: 9929748
    Abstract: Techniques and apparatus for verification of compressed data are described. In one embodiment, for example an apparatus to provide verification of compressed data may include at least one memory and logic, at least a portion of comprised in hardware coupled to the at least one memory, the logic to access compressed data, access compression information associated with the compressed data, decompress at least a portion of the compressed data to generate decompressed data, and verify the compressed data via a comparison of the decompressed data with the compression information. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 27, 2018
    Assignee: INTEL CORPORATION
    Inventors: Vinodh Gopal, James D. Guilford, Kirk S. Yap, Daniel F. Cutter, Wajdi K. Feghali
  • Patent number: 9929747
    Abstract: Technologies for high-performance single-stream data compression include a computing device that updates an index data structure based on an input data stream. The input data stream is divided into multiple chunks. Each chunk has a predetermined length, such as 136 bytes, and overlaps the previous chunk by a predetermine amount, such as eight bytes. The computing device processes multiple chunks in parallel using the index data to generate multiple token streams. The tokens include literal tokens and reference tokens that refer to matching data from earlier in the input data stream. The computing device thus searches for matching data in parallel. The computing device merges the token streams to generate a single output token stream. The computing device may merge a pair of tokens from two different chunks to generate one or more synchronized tokens that are output to the output token stream. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: March 27, 2018
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Daniel F. Cutter, Kirk S. Yap
  • Patent number: 9917689
    Abstract: One embodiment provides an apparatus. The apparatus includes a single instruction multiple data (SIMD) hash module configured to apportion at least a first portion of a message of length L to a number (S) of segments, the message including a plurality of sequences of data elements, each sequence including S data elements, a respective data element in each sequence apportioned to a respective segment, each segment including a number N of blocks of data elements and to hash the S segments in parallel, resulting in S segment digests, the S hash digests based, at least in part, on an initial value and to store the S hash digests; a padding module configured to pad a remainder, the remainder corresponding to a second portion of the message, the second portion related to the length L of the message, the number of segments and a block size; and a non-SIMD hash module configured to hash the padded remainder, resulting in an additional hash digest and to store the additional hash digest.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: March 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: Sean M. Gulley, Vinodh Gopal, Wajdi K. Feghali, James D. Guilford, Gilbert M. Wolrich, Kirk S. Yap
  • Patent number: 9917597
    Abstract: A processor includes a decoder to decode an instruction to compress an input data stream and an execution unit for executing the instruction. The execution unit to generate metadata for a current input of the input data stream, the metadata comprises a first hint based on a portion of a current input that represents the input data stream at a current offset, select a first pointer to identify a location in a history buffer in a hash chain, determine whether the metadata generated for the current input matches metadata previously generated for the first pointer, and filter the first pointer from a search for a best match for the current input in the history buffer based on the determination that at least a portion of the metadata for the current input does not match a portion of the metadata for the first pointer.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: March 13, 2018
    Assignee: Intel Corporation
    Inventors: Daniel F. Cutter, Vinodh Gopal, James D. Guilford
  • Patent number: 9917596
    Abstract: Technologies for data decompression include a computing device that reads a symbol tag byte from an input stream. The computing device determines whether the symbol can be decoded using a fast-path routine, and if not, executes a slow-path routine to decompress the symbol. The slow-path routine may include data-dependent branch instructions that may be unpredictable using branch prediction hardware. For the fast-path routine, the computing device determines a next symbol increment value, a literal increment value, a data length, and an offset based on the tag byte, without executing an unpredictable branch instruction. The computing device sets a source pointer to either literal data or reference data as a function of the tag byte, without executing an unpredictable branch instruction. The computing device may set the source pointer using a conditional move instruction. The computing device copies the data and processes remaining symbols. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: March 13, 2018
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, Sean M. Gulley, James D. Guilford
  • Patent number: 9916160
    Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: March 13, 2018
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Gilbert M. Wolrich, Wajdi K Feghali, Erdinc Ozturk, Martin G Dixon, Sean Mirkes, Bret L Toll, Maxim Loktyukhin, Mark C Davis, Alexandre J Farcy
  • Publication number: 20180060235
    Abstract: Memory compression devices, systems, and associated methods are provided and described. Such devices, systems, and methods increase the effective bandwidth and reduce power consumption of non-volatile memory subsystems.
    Type: Application
    Filed: August 30, 2016
    Publication date: March 1, 2018
    Applicant: Intel Corporation
    Inventors: Kirk S. Yap, Vinodh Gopal, James D. Guilford
  • Publication number: 20180052611
    Abstract: In one embodiment, an apparatus comprises a processor to receive a plurality of values of a data set, the data set comprising a first value, a second value, and a third value; calculate and store a first delta corresponding to the first value, wherein the first delta is equal to the difference between the first value and the second value; and calculate and store a second delta corresponding to the second value, wherein the second delta is equal to the difference between the second value and the third value.
    Type: Application
    Filed: August 18, 2016
    Publication date: February 22, 2018
    Applicant: Intel Corporation
    Inventors: James D. Guilford, Vinodh Gopal
  • Publication number: 20180026653
    Abstract: Technologies for efficiently compressing data with run detection include a compute device. The compute device is to produce a hash as a function of a symbol at a present position and a predefined number of symbols after the present position in an input stream, determine whether the symbol at the present position is part of a run, obtain, from a hash table, a chain of pointers to previous positions in the input stream associated with the hash, determine, as a function of whether the symbol is part of a run and to identify a matched string, a number of strings referenced by the chain of pointers to compare to a string associated with the present position in the input stream, and output, in response to an identification of a matched string, a reference to the matched string in a set of compressed output data.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 25, 2018
    Inventors: Daniel F. Cutter, Vinodh Gopal, James D. Guilford
  • Publication number: 20180024752
    Abstract: Technologies for low-latency compression in a data center are disclosed. In the illustrative embodiment, a storage sled compresses data with a low-latency compression algorithm prior to storing the data. The latency of the compression algorithm is less than the latency of the storage device, so that the latency of the storage and retrieval times are not significantly affected by the compression and decompression. In other embodiments, a compute sled may compress data with a low-latency compression algorithm prior to sending the data to a storage sled.
    Type: Application
    Filed: December 30, 2016
    Publication date: January 25, 2018
    Inventors: Steven C. Miller, Vinodh Gopal, Kirk S. Yap, James D. Guilford, Wajdi K. Feghali
  • Publication number: 20180026651
    Abstract: Technologies for performing low-latency decompression include a managed node to parse, in response to a determination that a read tree descriptor does not match a cached tree descriptor, the read tree descriptor to construct one or more tables indicative of codes in compressed data. Each code corresponds to a different symbol. The managed node is further to decompress the compressed data with the one or more tables and store the one or more tables in association with the read tree descriptor in a cache memory for subsequent use.
    Type: Application
    Filed: March 30, 2017
    Publication date: January 25, 2018
    Inventors: Vinodh Gopal, Daniel F. Cutter, James D. Guilford, Kirk S. Yap
  • Publication number: 20180026655
    Abstract: Technologies for performing speculative decompression include a managed node to decode a variable size code at a present position in compressed data with a deterministic decoder and concurrently perform speculative decodes over a range of subsequent positions in the compressed data, determine the position of the next code, determine whether the position of the next code is within the range, and output, in response to a determination that the position of the next code is within the range, a symbol associated with the deterministically decoded code and another symbol associated with a speculatively decoded code at the position of the next code.
    Type: Application
    Filed: March 30, 2017
    Publication date: January 25, 2018
    Inventors: Vinodh Gopal, James D. Guilford, Kirk S. Yap
  • Publication number: 20180026654
    Abstract: Technologies for high-performance single-stream data compression include a computing device that updates an index data structure based on an input data stream. The input data stream is divided into multiple chunks. Each chunk has a predetermined length, such as 136 bytes, and overlaps the previous chunk by a predetermine amount, such as eight bytes. The computing device processes multiple chunks in parallel using the index data to generate multiple token streams. The tokens include literal tokens and reference tokens that refer to matching data from earlier in the input data stream. The computing device thus searches for matching data in parallel. The computing device merges the token streams to generate a single output token stream. The computing device may merge a pair of tokens from two different chunks to generate one or more synchronized tokens that are output to the output token stream. Other embodiments are described and claimed.
    Type: Application
    Filed: December 30, 2016
    Publication date: January 25, 2018
    Inventors: Vinodh Gopal, James D. Guilford, Daniel F. Cutter, Kirk S. Yap
  • Publication number: 20180026656
    Abstract: Technologies for heuristic Huffman code generation include a computing device that generates a weighted list of symbols for a data block. The computing device determines a threshold weight and identifies one or more lightweight symbols in the list that have a weight less than or equal to the threshold weight. The threshold weight may be the average weight of all symbols with non-zero weight in the list. The computing device generates a balanced sub-tree of nodes for the lightweight symbols, with each lightweight symbol associated with a leaf node. The computing device adds the remaining symbols and the root of the balanced sub-tree to a heap and generates a Huffman code tree by processing the heap. The threshold weight may be adjusted to tune performance and compression ratio. Other embodiments are described and claimed.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 25, 2018
    Inventors: Vinodh Gopal, James D. Guilford
  • Publication number: 20180026652
    Abstract: Technologies for compressing data with multiple hash tables include a compute device. The compute device is to produce, for each of multiple string prefixes of different string prefix sizes, an associated hash. Each string prefix defines a set of consecutive symbols in a string that starts at a present position in an input stream of symbols. The compute device is also to write, to a different hash table for each string prefix size, a pointer to the present position in association with the associated hash. Each hash is usable as an index into the associated hash table to provide the present position of the string.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 25, 2018
    Inventors: Daniel F. Cutter, Vinodh Gopal, James D. Guilford
  • Patent number: 9876509
    Abstract: An example method to parallelize data decompression includes adjusting a first one of initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; and merging, by executing an instruction with the processor, first decoded data generated by decoding a first segment of the compressed data bitstream starting from the first adjusted starting position with second decoded data generated by decoding a second segment of the compressed data bitstream, the decoding of the second segment starting from a second position in the compressed data bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the compressed data bitstream.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: January 23, 2018
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Sudhir K. Satpathy, Sanu K. Mathew
  • Patent number: 9871535
    Abstract: A processing device includes an accelerator circuit to identify a byte in a byte stream, determine whether a first byte string starting from a first byte position of the byte matches a second byte string starting from a second byte position, responsive to determining that the first byte string matches the second byte string, generate a token comprising a first symbol encoding a length of the first byte string and a second symbol encoding a byte distance between the first byte position and the second byte position, and responsive to determining that the first byte string does not match another byte string, generate the token comprising the first symbol comprising the byte and a second symbol encoding a determined value.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: January 16, 2018
    Assignee: Intel Corporation
    Inventors: James D. Guilford, Vinodh Gopal, Gilbert M. Wolrich, Daniel F. Cutter
  • Publication number: 20180011656
    Abstract: A processing system is provided that includes a memory for storing an input bit stream and a processing logic, operatively coupled to the memory, to generate a first score based on: a first set of matching data related to a match between a first bit subsequence and a candidate bit subsequence within the input bit stream, and a first distance of the candidate bit subsequence from the first set of matching data. A second score is generated based on a second set of matching data related to a match between a second bit subsequence and the candidate bit subsequence, and a second distance of the candidate bit subsequence from the second set of matching data. A code to replace the first or second bit subsequence in an output bit stream is identified. Selection of the one of the bit subsequences to replace is based on a comparison of the scores.
    Type: Application
    Filed: July 28, 2017
    Publication date: January 11, 2018
    Inventors: James D. Guilford, Vinodh Gopal, Gilbert M. Wolrich, Daniel F. Cutter
  • Publication number: 20180011796
    Abstract: A processor includes a memory hierarchy, buffer, and a decompressor. The decompressor includes circuitry to read elements to be decompressed according to a compression scheme, parse the elements to identify literals and matches, and, with the literals and matches, generate an intermediate token stream formatted for software-based copying of the literals and matches to produce decompressed data. The intermediate token stream is to include a format for multiple tokens that are to be written in parallel with each other, and another format for tokens that include a data dependency upon themselves.
    Type: Application
    Filed: July 5, 2016
    Publication date: January 11, 2018
    Inventors: James D. Guilford, Vinodh Gopal, Kirk S. Yap