Patents by Inventor James D. Huey

James D. Huey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8250203
    Abstract: Method and system for collecting diagnostic information for network communication is provided. The method includes configuring a host bus adapter (HBA) to operate as a standard HBA while collecting diagnostic information in a diagnostic mode after a trigger condition occurs; storing the diagnostic information in a first memory for the HBA; transferring the diagnostic information from the first memory to a second memory in a host system that is operationally coupled to the HBA; and formatting the diagnostic information for presentation to a user.
    Type: Grant
    Filed: May 22, 2007
    Date of Patent: August 21, 2012
    Assignee: QLOGIC, Corporation
    Inventor: James D. Huey
  • Patent number: 7669190
    Abstract: A host bus adapter (“HBA”) is provided with a programmable trace logic that can be enabled or disabled by firmware running on the HBA and if enabled can receive trace information from at least one processor, which is stored in a local memory buffer controlled by a local memory interface. A receive and transmit path processor data is traced and stored in the local memory buffer. The trace logic includes an arbitration module that receives trace data from plural sources and the trace data is stored in a first in first out based buffer before being sent to a direct memory access arbiter module and then to an external memory. Trace data as stored in the external memory includes a trace data source identity value, and a time stamp value indicating when data was collected.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: February 23, 2010
    Assignee: QLOGIC, Corporation
    Inventors: Dharma R. Konda, James D. Huey, Frank W. Campbell, Tuan A. Doan
  • Patent number: 5491793
    Abstract: A central processing unit (CPU) with facilities for debug support. The debug support facilities include debug support unit (DSU), a debug support interface bus, and a diagnostic instrument. During an execution trace, the DSU transmits trace data such as an instruction address and a trace status via the bus to the diagnostic instrument. Instruction addresses are sent in 4-bit segments in one clock cycle during a trace. Trace status includes an indication of non-sequential instruction execution by the Instruction Unit (IU). A control bit is used to toggle a hold on IU operation where a non-sequential instruction is encountered in trace mode. The diagnostic instrument uses trace data provided by the DSU to generate a complete execution trace in real-time. During breakpoint operations, input such as a debug instruction is provided by the diagnostic instrument via the debug support interface bus to the CPU for execution thereby.
    Type: Grant
    Filed: October 11, 1994
    Date of Patent: February 13, 1996
    Assignee: Fujitsu Limited
    Inventors: M. Somasundaram, Akira Watanabe, James D. Huey, Dinesh Maheshwari