Patents by Inventor James D. Jackson

James D. Jackson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10555417
    Abstract: Disclosed are embodiments of a system-level assembly including an integrated circuit (IC) die directly attached to a mainboard. An IC die directly attached to a mainboard or other circuit board may be referred to as a direct-chip attach (DCA) die. A package is disposed over at least a portion of the DCA die and coupled with the mainboard. The package includes one or more other IC die disposed on a substrate. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Damion Searls, Weston C. Roth, Margaret D. Ramirez, James D. Jackson, Rainer E. Thomas, Charles A. Gealer
  • Publication number: 20190182958
    Abstract: Disclosed are embodiments of a system-level assembly including an integrated circuit (IC) die directly attached to a mainboard. An IC die directly attached to a mainboard or other circuit board may be referred to as a direct-chip attach (DCA) die. A package is disposed over at least a portion of the DCA die and coupled with the mainboard. The package includes one or more other IC die disposed on a substrate. Other embodiments are described and claimed.
    Type: Application
    Filed: February 20, 2019
    Publication date: June 13, 2019
    Inventors: Damion SEARLS, Weston C. ROTH, Margaret D. RAMIREZ, James D. JACKSON, Rainer E. THOMAS, Charles A. GEALER
  • Patent number: 10251273
    Abstract: Disclosed are embodiments of a system-level assembly including an integrated circuit (IC) die directly attached to a mainboard. An IC die directly attached to a mainboard or other circuit board may be referred to as a direct-chip attach (DCA) die. A package is disposed over at least a portion of the DCA die and coupled with the mainboard. The package includes one or more other IC die disposed on a substrate. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Damion Searls, Weston C. Roth, Margaret D. Ramirez, James D. Jackson, Rainer E. Thomas, Charles A. Gealer
  • Publication number: 20150087461
    Abstract: The present invention is directed to a Banjo type axle assembly with a drop out third member carrier for the pinion shaft assembly, ring gear assembly, the rotatable differential house assembly and the differential bearing clamp assembly. Said drop out third member carrier and the rear axle housing are constructed sufficiently to house a 10.5 inch diameter ring gear. In one preferred embodiment the drive pinion assembly and the ring gear assembly exhibit a mild hypoid gear set orientation. In one preferred embodiment said drop out third member carrier has substantially uniform dimensions in thickness and has a symmetrical bolt pattern between a pinion shaft side and a non-pinion shaft side with a total of twelve bolts to affix said drop out third member to carrier to said rear axle housing. An oiling shelf has extra material to house pinion bolts as part of the pinion shaft assembly.
    Type: Application
    Filed: September 21, 2013
    Publication date: March 26, 2015
    Inventors: James D. Jackson, Phillip A. Rawlings
  • Publication number: 20120224331
    Abstract: A standoff contact array is disposed between a mounting substrate of a flip-chip package and a board. The standoff contact array is formable by mating a low-profile solder bump on the mounting substrate with a low-profile solder paste on the board. Thereafter, the standoff contact array is formed by reflowing the low-profile solder paste on the board against the low-profile solder bump on the mounting substrate.
    Type: Application
    Filed: May 17, 2012
    Publication date: September 6, 2012
    Inventors: Weston Roth, Kevin Byrd, Damion Searls, James D. Jackson
  • Patent number: 7791585
    Abstract: A method of fabricating a flexible display, the method comprising selecting a first flexible sheet and a second flexible sheet; and forming a number of magnetic display elements having magnetically controllable reflectivity between the first flexible sheet and the second flexible sheet. In some embodiments, a display includes pixels having a magnetically controllable reflectivity. The pixels are formed between a pair of flexible non-conductive sheets. Each of the magnetically controllable pixels includes a flexible ring located between the flexible non-conductive sheets. Each of the magnetically controllable pixels also includes magnetic particles located within the flexible ring. The location of the magnetic particles with respect to the flexible non-conductive sheets determines the reflectivity of the pixel. The display is especially suitable for use in connection with portable electronic devices.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: September 7, 2010
    Assignee: Intel Corporation
    Inventors: James D. Jackson, Terrance J. Dishongh, Damion T. Searls
  • Publication number: 20100061056
    Abstract: Disclosed are embodiments of a system-level assembly including an integrated circuit (IC) die directly attached to a mainboard. An IC die directly attached to a mainboard or other circuit board may be referred to as a direct-chip attach (DCA) die. A package is disposed over at least a portion of the DCA die and coupled with the mainboard. The package includes one or more other IC die disposed on a substrate. Other embodiments are described and claimed.
    Type: Application
    Filed: September 8, 2008
    Publication date: March 11, 2010
    Inventors: Damion Searls, Weston C. Roth, Margaret D. Ramirez, James D. Jackson, Rainer E. Thomas, Charles A. Gealer
  • Patent number: 7638884
    Abstract: A thin semiconductor device package, comprising a thin substrate at least one thin die coupled with the substrate and having a perimeter dimension less than that of the substrate a mold material provided at a surface of the substrate adjacent to the perimeter of the die so that a surface of the mold material is coplanar with a surface of the die, and at least one electrically conductive pathway having at least one first terminal end configured to provide electrical continuity with the conductive element and at least one second terminal end formed at a surface of the mold material, the pathway extending from the first terminal end to the second terminal end.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: December 29, 2009
    Assignee: Intel Corporation
    Inventors: James D. Jackson, Damion T. Searls, Yoshihiro Tomita
  • Publication number: 20090310320
    Abstract: A standoff contact array is disposed between a mounting substrate of a flip-chip package and a board. The standoff contact array is formable by mating a low-profile solder bump on the mounting substrate with a low-profile solder paste on the board. Thereafter, the standoff contact array is formed by reflowing the low-profile solder paste on the board against the low-profile solder bump on the mounting substrate.
    Type: Application
    Filed: June 16, 2008
    Publication date: December 17, 2009
    Inventors: Weston Roth, Kevin Byrd, Damion Searls, James D. Jackson
  • Publication number: 20090109643
    Abstract: A thin semiconductor device package, comprising a thin substrate at least one thin die coupled with the substrate and having a perimeter dimension less than that of the substrate a mold material provided at a surface of the substrate adjacent to the perimeter of the die so that a surface of the mold material is coplanar with a surface of the die, and at least one electrically conductive pathway having at least one first terminal end configured to provide electrical continuity with the conductive element and at least one second terminal end formed at a surface of the mold material, the pathway extending from the first terminal end to the second terminal end.
    Type: Application
    Filed: January 5, 2009
    Publication date: April 30, 2009
    Inventors: James D. Jackson, Damion T. Searls, Yoshihiro Tomita
  • Patent number: 7517732
    Abstract: A thin semiconductor device package, comprising a thin substrate, at least one thin die coupled with the substrate and having a perimeter dimension less than that of the substrate, a mold material provided at a surface of the substrate adjacent to the perimeter of the die so that a surface of the mold material is coplanar with a surface of the die, and at least one electrically conductive pathway having at least one first terminal end configured to provide electrical continuity with the conductive element and at least one second terminal end formed at a surface of the mold material, the pathway extending from the first terminal end to the second terminal end.
    Type: Grant
    Filed: April 12, 2006
    Date of Patent: April 14, 2009
    Assignee: Intel Corporation
    Inventors: James D. Jackson, Damion T. Searls, Yoshihiro Tomita
  • Publication number: 20090051004
    Abstract: A microelectronic package and a method of forming the package. The package includes a first level package mounted to a carrier. The first level package includes a package substrate having a die side and a carrier side; and a microelectronic die mounted on the package substrate at the die side thereof. The carrier has a substrate side, and the first level package is mounted on the carrier at the substrate side thereof. A rigid body is attached to the carrier side of the substrate at an attachment location of the substrate and to the substrate side of the carrier at an attachment location of the carrier, the attachment location of the carrier being electrically unconnected, the rigid body being configured and disposed to provide structural support between the substrate and the carrier.
    Type: Application
    Filed: August 24, 2007
    Publication date: February 26, 2009
    Inventors: Weston C. Roth, James D. Jackson, Damion Searls, Kevin Byrd
  • Patent number: 7495318
    Abstract: The invention relates to an apparatus and method for improving AC coupling between adjacent signal traces and between plane splits and signals spanning plane splits on circuit boards. A circuit board includes adjacent conductive means and an oxide means interposed there between. The oxide means is a copper oxide, e.g., cupric or cuprous oxide. In one embodiment, the adjacent conductive means are adjacent voltage reference planes with a split interposed between the conductive means. The copper oxide fills the split. In another embodiment, the adjacent conductive means are differential signal traces. The copper oxide fills a gap between the differential signal traces. The copper oxide is a non-conductive material with an increased dielectric constant as compared to other common dielectric materials used as fillers. The increased dielectric constant increases capacitance, in turn, increasing AC coupling.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: February 24, 2009
    Assignee: Intel Corporation
    Inventors: Weston Roth, Damion T. Searls, James D. Jackson
  • Patent number: 7361988
    Abstract: Various methods and apparatuses are described in which a printed circuit board has trace lines. Input/output pads on the printed circuit board may have approximately the same width dimension as a trace line connected to those input/output pads. A first group of vias in the printed circuit board may be aligned into a planar line with a set corridor spacing between adjacent of groups of vias also aligned into a planar line with the same axis to allow a routing space for lines in multiple layers of the printed circuit board to occur in the routing space established by the set corridor spacing.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: April 22, 2008
    Assignee: Intel Corporation
    Inventors: Thomas O. Morgan, James D. Jackson, Weston C. Roth
  • Patent number: 7255492
    Abstract: A method includes providing a light pipe having a metallized end surface, and soldering the metallized end surface of the light pipe to a surface of a substrate. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 2, 2004
    Date of Patent: August 14, 2007
    Assignee: Intel Corporation
    Inventors: Weston C. Roth, Damion T. Searls, Thomas O. Morgan, James D. Jackson
  • Patent number: 7158111
    Abstract: A display includes pixels having a magnetically controllable reflectivity. The pixels are formed between a pair of flexible non-conductive sheets. Each of the magnetically controllable pixels includes a flexible ring located between the flexible non-conductive sheets. Each of the magnetically controllable pixels also includes magnetic particles located within the flexible ring. The location of the magnetic particles with respect to the flexible non-conductive sheets determines the reflectivity of the pixel. The display is especially suitable for use in connection with portable electronic devices.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: January 2, 2007
    Assignee: Intel Corporation
    Inventors: James D. Jackson, Terrance J. Dishongh, Damion T. Searls
  • Patent number: 6996899
    Abstract: Solder bumps are created on a substrate of an electronic assembly having lengths that are longer than the widths. The solder bumps are created by locating solder balls of power or ground connections close to one another so that, upon reflow, the solder balls combine. Signal solder balls however remain separated. Capacitors are created by locating power solder bumps adjacent ground solder bumps and extending parallel to one another.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: February 14, 2006
    Assignee: Intel Corporation
    Inventors: Damion T. Searls, Terrance J. Dishongh, James D. Jackson
  • Patent number: 6905979
    Abstract: The invention relates to an apparatus and method for improving AC coupling between adjacent signal traces and between plane splits and signals spanning plane splits on circuit boards. A circuit board includes adjacent conductive means and an oxide means interposed there between. The oxide means is a copper oxide, e.g., cupric or cuprous oxide. In one embodiment, the adjacent conductive means are adjacent voltage reference planes with a split interposed between the conductive means. The copper oxide fills the split. In another embodiment, the adjacent conductive means are differential signal traces. The copper oxide fills a gap between the differential signal traces. The copper oxide is a non-conductive material with an increased dielectric constant as compared to other common dielectric materials used as fillers. The increased dielectric constant increases capacitance, in turn, increasing AC coupling.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: June 14, 2005
    Assignee: Intel Corporation
    Inventors: Weston Roth, Damion T. Searls, James D. Jackson
  • Publication number: 20040119147
    Abstract: The invention relates to an apparatus and method for improving AC coupling between adjacent signal traces and between plane splits and signals spanning plane splits on circuit boards. A circuit board includes adjacent conductive means and an oxide means interposed there between. The oxide means is a copper oxide, e.g., cupric or cuprous oxide. In one embodiment, the adjacent conductive means are adjacent voltage reference planes with a split interposed between the conductive means. The copper oxide fills the split. In another embodiment, the adjacent conductive means are differential signal traces. The copper oxide fills a gap between the differential signal traces. The copper oxide is a non-conductive material with an increased dielectric constant as compared to other common dielectric materials used as fillers. The increased dielectric constant increases capacitance, in turn, increasing AC coupling.
    Type: Application
    Filed: December 23, 2002
    Publication date: June 24, 2004
    Applicant: Intel Corporation
    Inventors: Weston Roth, Damion T. Searls, James D. Jackson
  • Patent number: 6730860
    Abstract: Solder bumps are created on a substrate of an electronic assembly having lengths that are longer than the widths. The solder bumps are created by locating solder balls of power or ground connections close to one another so that, upon reflow, the solder balls combine. Signal solder balls however remain separated. Capacitors are created by locating power solder bumps adjacent ground solder bumps and extending parallel to one another.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: May 4, 2004
    Assignee: Intel Corporation
    Inventors: Damion T. Searls, Terrance J. Dishongh, James D. Jackson