Patents by Inventor James D. Jarratt
James D. Jarratt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7703194Abstract: A method for creating a write element of a magnetic head according to one embodiment includes forming a first pole pedestal; forming a write gap layer above the first pole pedestal; forming a second pole pedestal above the write gap layer; and forming at least one of: a cap layer of CoFeON between the first pole pedestal and the write gap, and a seed layer of CoFeON between the write gap layer and the second pole pedestal. Note that other layers may be interspersed between those set forth here.Type: GrantFiled: March 19, 2007Date of Patent: April 27, 2010Assignee: International Business Machines CorporationInventors: Brian E. Brusca, Joel S. Forrest, Richard Hsiao, James D. Jarratt, Brian R. York
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Patent number: 7397634Abstract: A system and method are provided for manufacturing a coil structure for a magnetic head. Initially, an insulating layer is deposited with a photoresist layer deposited on the insulating layer. Moreover, a silicon dielectric layer is deposited on the photoresist layer as a hard mask. The silicon dielectric layer is then masked. A plurality of channels is subsequently formed in the silicon dielectric layer using reactive ion etching (i.e. CF4/CHF3). The silicon dielectric layer is then used as a hard mask to transfer the channel pattern in the photoresist layer using reactive ion etching with, for example, H2/N2/CH3F/C2H4 reducing chemistry. To obtain an optimal channel profile with the desired high aspect ratio, channel formation includes a first segment defining a first angle and a second segment defining a second angle. Thereafter, a conductive seed layer is deposited in the channels and the channels are filled with a conductive material to define a coil structure.Type: GrantFiled: June 23, 2003Date of Patent: July 8, 2008Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Daniel Wayne Bedell, Richard Hsiao, James D. Jarratt, Patrick Rush Webb, Sue Siyang Zhang
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Patent number: 7380332Abstract: A system and method are provided for manufacturing a coil structure for a magnetic head. Initially, an insulating layer is deposited with a photoresist layer deposited on the insulating layer. Moreover, a silicon dielectric layer is deposited on the photoresist layer as a hard mask. The silicon dielectric layer is then masked. A plurality of channels is subsequently formed in the silicon dielectric layer using reactive ion etching (i.e. CF4/CHF3). The silicon dielectric layer is then used as a hard mask to transfer the channel pattern in the photoresist layer using reactive ion etching with, for example, H2/N2/CH3F/C2H4 reducing chemistry. To obtain an optimal channel profile with the desired high aspect ratio, channel formation includes a first segment defining a first angle and a second segment defining a second angle. Thereafter, a conductive seed layer is deposited in the channels and the channels are filled with a conductive material to define a coil structure.Type: GrantFiled: January 20, 2005Date of Patent: June 3, 2008Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Daniel Wayne Bedell, Richard Hsiao, James D. Jarratt, Patrick Rush Webb, Sue Siyang Zhang
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Patent number: 7233458Abstract: A write element includes a first pole pedestal and a second pole pedestal opposing the first pole pedestal and defining a write gap between the first and second pole pedestals. A first layer of CoFeON is film positioned between the first pole pedestal and the write gap. A second layer of CoFeON film is positioned between the second pole pedestal and the write gap.Type: GrantFiled: September 11, 2002Date of Patent: June 19, 2007Assignee: International Business Machines CorporationInventors: Brian E. Brusca, Joel S. Forrest, Richard Hsiao, James D. Jarratt, Brian R. York
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Patent number: 7108796Abstract: A method for fabrication of magnetic write heads for disk drives in which a P1 layer is formed having a P1 Protrusion, the P1 Protrusion having a longitudinal reference axis. A gap layer is deposited on the P1 Protrusion and a layer of fill material is deposited on the gap layer. The fill material layer is shaped to form a mold which surrounds a hollow which is aligned with the longitudinal axis of the P1 Protrusion. This hollow in the fill material layer is filled with P2 pole material to form a P2 pole which is then automatically substantially aligned with the longitudinal axis of the P1 Protrusion.Type: GrantFiled: September 30, 2003Date of Patent: September 19, 2006Assignee: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Christopher W. Bergevin, James D. Jarratt, Jyh-Shuey Jerry Lo, Sue Siyang Zhang
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Patent number: 6944937Abstract: The present invention provides a method of manufacturing a magnetoresistive read head which reduces electrostatic discharge and allows measurement of gap resistances in the head.Type: GrantFiled: June 30, 2003Date of Patent: September 20, 2005Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Richard Hsiao, James D. Jarratt, Emo Hilbrand Klaassen, Ian Robson McFadyen, Timothy J. Moran
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Publication number: 20040257701Abstract: A system and method are provided for manufacturing a coil structure for a magnetic head. Initially, an insulating layer is deposited with a photoresist layer deposited on the insulating layer. Moreover, a silicon dielectric layer is deposited on the photoresist layer as a hard mask. The silicon dielectric layer is then masked. A plurality of channels is subsequently formed in the silicon dielectric layer using reactive ion etching (i.e. CF4/CHF3). The silicon dielectric layer is then used as a hard mask to transfer the channel pattern in the photoresist layer using reactive ion etching with, for example, H2/N2/CH3F/C2H4 reducing chemistry. To obtain an optimal channel profile with the desired high aspect ratio, channel formation includes a first segment defining a first angle and a second segment defining a second angle. Thereafter, a conductive seed layer is deposited in the channels and the channels are filled with a conductive material to define a coil structure.Type: ApplicationFiled: June 23, 2003Publication date: December 23, 2004Applicant: HITACHI GLOBAL STORAGE TECHNOLOGIES, INC.Inventors: Daniel Wayne Bedell, Richard Hsiao, James D. Jarratt, Patrick Rush Webb, Sue Siyang Zhang
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Publication number: 20040090715Abstract: A first read gap layer has a resistance RG1 between a first shield layer and one of the first and second lead layers of a read head and the second read gap layer has a resistance RG2 between a second shield layer and said one of the first and second lead layers of the read head. A connection is provided via a plurality of resistors between a first node and each of the first and second shield layers wherein the plurality of resistors includes at least first and second resistors RS1 and RS2 and the first node is connected to said one of the first and second lead layers. A second node is located between the first and second resistors RS1 and RS2. An operational amplifier has first and second inputs connected to the first and second nodes respectively so as to be across the first resistor RS1 and has an output connected to the first node for maintaining the first and second nodes at a common voltage potential. In a first embodiment the first and second shield layers are shorted together.Type: ApplicationFiled: June 30, 2003Publication date: May 13, 2004Applicant: Hitachi Global Storage TechnologiesInventors: Richard Hsiao, James D. Jarratt, Emo Hilbrand Klaassen, Ian Robson McFadyen, Timothy J. Moran
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Publication number: 20040047072Abstract: A write element includes a first pole pedestal and a second pole pedestal opposing the first pole pedestal and defining a write gap between the first and second pole pedestals. A first layer of CoFeON is film positioned between the first pole pedestal and the write gap. A second layer of CoFeON film is positioned between the second pole pedestal and the write gap.Type: ApplicationFiled: September 11, 2002Publication date: March 11, 2004Applicant: INTERNATIONAL BUSINESS MACHINESInventors: Brian E. Brusca, Joel S. Forrest, Richard Hsiao, James D. Jarratt, Brian R. York
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Patent number: 6678127Abstract: A first read gap layer has a resistance RG1 between a first shield layer and one of the first and second lead layers of a read head and the second read gap layer has a resistance RG2 between a second shield layer and said one of the first and second lead layers of the read head. A connection is provided via a plurality of resistors between a first node and each of the first and second shield layers wherein the plurality of resistors includes at least first and second resistors RS1 and RS2 and the first node is connected to said one of the first and second lead layers. A second node is located between the first and second resistors RS1 and RS2. An operational amplifier has first and second inputs connected to the first and second nodes respectively so as to be across the first resistor RS1 and has an output connected to the first node for maintaining the first and second nodes at a common voltage potential. In a first embodiment the first and second shield layers are shorted together.Type: GrantFiled: January 2, 2001Date of Patent: January 13, 2004Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Richard Hsiao, James D. Jarratt, Emo Hilbrand Klaassen, Ian Robson McFadyen, Timothy J. Moran
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Publication number: 20020085318Abstract: A first read gap layer has a resistance RG1 between a first shield layer and one of the first and second lead layers of a read head and the second read gap layer has a resistance RG2 between a second shield layer and said one of the first and second lead layers of the read head. A connection is provided via a plurality of resistors between a first node and each of the first and second shield layers wherein the plurality of resistors includes at least first and second resistors RS1 and RS2 and the first node is connected to said one of the first and second lead layers. A second node is located between the first and second resistors RS1 and RS2. An operational amplifier has first and second inputs connected to the first and second nodes respectively so as to be across the first resistor RS1 and has an output connected to the first node for maintaining the first and second nodes at a common voltage potential. In a first embodiment the first and second shield layers are shorted together.Type: ApplicationFiled: January 2, 2001Publication date: July 4, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Richard Hsiao, James D. Jarratt, Emo Hilbrand Klaassen, Ian Robson McFadyen, Timothy J. Moran