Abstract: A node comprises at least one agent and an input/output (I/O) circuit coupled to an interconnect within the node. The I/O circuit is configured to communicate on a global interconnect to which one or more other nodes are coupled during use. Addresses transmitted on the interconnect are in a first local address space of the node, and addresses transmitted on the global interconnect are in a global address space. The first local address space includes at least a first region used to address at least a first resource of the node. The node is programmable, during use, to relocate the first region within the first local address space, whereby a same numerical value in the first local address space and a second local address space corresponding to one of the other nodes coupled to the global interconnect refers to the first resource in the node during use.

Abstract: A method for treating IL-20 induced inflammation. An antagonist to IL-20 is administered to treat inflammation and associated diseases. The antagonist can be an antibody that binds to IL-20 or its receptor or a soluble receptor that binds to IL-20. Examples of such diseases are adult respiratory disease, psoriasis, eczema, contact dermatitis, atopic dermatitis, septic shock, multiple organ failure, inflammatory lung injury, bacterial pneumonia, inflammatory bowel disease, rheumatoid arthritis, asthma, ulcerative colitis and Crohn's disease.

Abstract: The present invention provides novel purified and isolated nucleic acid sequences associated with disease resistance and tolerance in plants. Methods of using the nucleic acid sequences to confer disease resistance and tolerance to plants are also provided.

Abstract: A method for treating IL-20 induced inflammation. An antagonist to IL-20 is administered to treat inflammation and associated diseases. The antagonist can be an antibody that binds to IL-20 or its receptor or a soluble receptor that binds to IL-20. Examples of such diseases are adult respiratory disease, psoriasis, eczema, contact dermatitis, atopic dermatitis, septic shock, multiple organ failure, inflammatory lung injury, bacterial pneumonia, inflammatory bowel disease, rheumatoid arthritis, asthma, ulcerative colitis and Crohn's disease.

Abstract: The use of corticotroph-derived glycoprotein hormone (CGH) to induce lipolysis, treat obesity, insulin resistance, and type II diabetes is described.

Abstract: The present invention provides novel purified and isolated nucleic acid sequences associated with disease resistance and tolerance in plants. Methods of using the nucleic acid sequences to confer disease resistance and tolerance to plants are also provided.

Abstract: A method for treating IL-20 induced inflammation. An antagonist to IL-20 is administered to treat inflammation and associated diseases. The antagonist can be an antibody that binds to IL-20 or its receptor or a soluble receptor that binds to IL-20. Examples of such diseases are adult respiratory disease, psoriasis, eczema, contact dermatitis, atopic dermatitis, septic shock, multiple organ failure, inflammatory lung injury, bacterial pneumonia, inflammatory bowel disease, rheumatoid arthritis, asthma, ulcerative colitis and Crohn's disease.

Abstract: In a computer memory system, memory access operations are significantly enhanced by employing a data path between the read only memory (ROM) and the system processor that is separate and independent from the data path or paths between the system processor and the random access memory (i.e., RAM or DRAM). The separate ROM data path includes a full cache line buffer which stores the ROM data until the system data bus is available to transport the ROM data. With a separate ROM data path, that includes a full cache line buffer, memory access operations are more efficiently conducted because a RAM access (i.e., a read or write operation) and a ROM access (i.e., a read operation) can be executed concurrently.

Abstract: Dimeric proteins having substantially the same biological activity as PDGF are disclosed. More specifically, the protein may have two substantially identical polypeptide chains, each of the chains being substantially homologous to the A-chain of PDGF. Alternatively, the protein may have two polypeptide chains that are substantially identical to the A-chain of PDGF. In addition, proteins comprising polypeptides that are variants or derivatives of the A-chain of PDGF are also disclosed. Therapeutic compositions containing these proteins and methods for enhancing the wound-healing process in warm-blooded animals are also disclosed.

Abstract: A mechanism is provided for reordering bus transactions to increase bus utilization in a computer system in which a split-transaction bus is bridged to a single-envelope bus. In one embodiment, both masters and slaves are ordered, simplifying implementation. In another embodiment, the system is more loosely coupled with only masters being ordered. Greater bus utilization is thereby achieved. To avoid deadlock, transactions begun on the split-transaction bus are monitored. When a combination of transactions would, if a predetermined further transaction were to begin, result in deadlock, this condition is detected. In the more tightly coupled system, the predetermined further transaction, if it is requested, is refused, thereby avoiding deadlock. In the more loosely-coupled system, the flexibility afforded by unordered slaves is taken advantage of to, in the typical case, reorder the transactions and avoid deadlock without killing any transaction.

Abstract: A computer system in which interrupt signals are serially transmitted from an input/output (I/O) controller is disclosed. The I/O controller initially receives the interrupt signals and then serially transmits them to an interrupt controller where the received interrupt signals are managed. According to the invention, the sequencing by which the interrupt signals are serially transmitted is controlled such that it largely conforms to the sequencing by which the received interrupt signals are processed at the interrupt controller, thereby controlling and reducing latency. The interrupt controller can be a separate integrated circuit chip or integral to another integrated circuit chip of the computer system.

Abstract: A mechanism is provided for avoiding deadlock in a computer system in which a split-transaction bus is bridged to a single-envelope bus. In one embodiment, transactions begun on said split-transaction bus are monitored. When a combination of transactions would, if a predetermined further transaction were to begin, result in deadlock, this condition is detected. The predetermined further transaction, if it is requested, is refused, thereby avoiding deadlock. In accordance with another embodiment of the invention, the bus bridge detects when a state of the split-transaction bus would, if a protocol of said split-transaction bus were adhered to, result in deadlock. The bus bridge then drives one or more signals on the split-transaction bus in disregard of the protocol of the split-transaction bus, thereby avoiding deadlock. In accordance with still a further embodiment of the invention, transactions accepted within the bus bridge are monitored.

Abstract: A mechanism is provided for reordering bus transactions to increase bus utilization in a computer system in which a split-transaction bus is bridged to a single-envelope bus. In one embodiment, both masters and slaves are ordered, simplifying implementation. In another embodiment, the system is more loosely coupled with only masters being ordered. Greater bus utilization is thereby achieved. To avoid deadlock, transactions begun on said split-transaction bus are monitored. When a combination of transactions would, if a predetermined further transaction were to begin, result in deadlock, this condition is detected. In the more tightly coupled system, the predetermined further transaction, if it is requested, is refused, thereby avoiding deadlock. In the more loosely-coupled system, the flexibility afforded by unordered slaves is taken advantage of to, in the typical case, reorder the transactions and avoid deadlock without killing any transaction.

Abstract: A bus bridge circuit employs a dynamic allocation scheme that allows read transactions to be pipelined without deadlock and without the need for permanently reserving multiple buffer slots for read response transactions. The bus bridge circuit associates input and output buffers with a node and includes a state machine to monitor the number and type of transaction packets currently in slots that make up the buffers. In particular, the state machine monitors the number of transaction packets loaded in the output buffer slots, the number of outstanding read transactions for the node, and the number of read response transactions currently loaded in the output buffer. The state machine then allows the node to load a READ or WRITE transaction only if the monitored data indicates at least one of the buffer slots will be available to service a READ RESPONSE subsequently loaded by the node.

Abstract: A data system architecture and interface circuits permit slow devices having limited signal capacities to launch and receive information from a central bus. Data is clocked onto the bus with a master circuit at the leading and trailing edges of the bus clock so that portions of a large multibit signal are launched without having to wait for the initiation of a next clock cycle. Accordingly, data portions are launched during both leading and trailing edges of the clock signal. In the case of a simple bus device not able to accommodate inclusion of a slave interface circuit, the received signal packet is provided in adapted form anticipating that only a second half portion of the signal packet will actually be registered as received.

Abstract: To optimize system bus utilization in a computer system, a bus coordinator is included in the computer system to coordinate the transfer of information signals on the bus. Each time a source node wishes to transfer information to a destination node, the source node sends a request to the coordinator along with the identification of the destination node. Upon receiving this request, the coordinator determines whether the destination node has capacity to receive information signals. If the destination node has capacity, then the coordinator grants control of the system bus to the source node to allow the source node to send information signals to the destination node via the system bus. Otherwise, the source node is denied control of the system bus until the destination node has capacity to receive information signals.

Abstract: Isolated DNA molecules that encode a novel PDGF receptor are disclosed. The receptor binds the AA, AB and BB isoforms of PDGF with high affinity. Cells transfected or transformed with the DNA molecules are also disclosed. The cells can be used within methods for detecting PDGF agonist or antagonist activity in a test compound.

Abstract: The present invention, generally speaking, provides a system and method of decoupling the address and data buses of a system bus using side band information signals. A computer system with which the invention may be used has a system bus including an address bus and a data bus and has, operatively connected to said system bus, multiple master devices, including a microprocessor, and multiple slave devices. In accordance with one embodiment of the invention, the address bus and the data bus are decoupled by providing, in addition to signals carried by the system bus, first side-band signals including, for each master device besides the microprocessor, an address arbitration signal, and providing, in addition to signals carried by the system bus, second side-band signals including, for each slave device, an address termination signal, a data arbitration signal, and a read-ready signal indicating that a respective slave device has data to present on the system bus.

Abstract: A bus system uses separate clocks for arbitration and data transfer. The arbitration clock signal is used for synchronizing bus request and grant events, and the data clock signal is used for synchronizing data transmission and reception. In particular, the data clock signal, which is generated by a bus master node without any temporal relationship to the arbitration clock signal, is transmitted by the bus master node through the bus to a slave node, where the received data signal is synchronized with the data clock signal transmitted therewith.

Abstract: A mechanism is provided for reordering bus transactions to increase bus utilization in a computer system in which a split-transaction bus is bridged to a single-envelope bus. In one embodiment, both masters and slaves are ordered, simplifying implementation. In another embodiment, the system is more loosely coupled with only masters being ordered. Greater bus utilization is thereby achieved. To avoid deadlock, transactions begun on the split-transaction bus are monitored. When a combination of transactions would, if a predetermined further transaction were to begin, result in deadlock, this condition is detected. In the more tightly coupled system, the predetermined further transaction, if it is requested, is refused, thereby avoiding deadlock. In the more loosely-coupled system, the flexibility afforded by unordered slaves is taken advantage of to, in the typical case, reorder the transactions and avoid deadlock without killing any transaction.