Patents by Inventor James D. McCollum

James D. McCollum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10095590
    Abstract: A fault tolerant computer system having two virtual machines (VMs), each running on a separate host device, is connected over a network to one or more I/O devices. The system operates to monitor the health of one or more operational characteristics associated with each VM, and in the event that the health of both virtual machines dictates that one or the other of the VMs should be downgraded, but the system is not able to determine which VM should be downgraded and there is an imbalance in a monitored system operational characteristic, the system can defer downgrading one VM for a selected period of time during which the operational characteristic that is in imbalance is monitored. If the imbalance is resolved, the downgrade is cancelled, if an operational fault is confirmed prior to the expiration of the deferral period or if the deferral period expires, then one host is downgraded.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: October 9, 2018
    Inventors: Thomas D Bissett, Stephen J Wark, Paul A Leveille, James D McCollum, Angel L Pagan
  • Publication number: 20160328302
    Abstract: A fault tolerant computer system having two virtual machines (VMs), each running on a separate host device, is connected over a network to one or more I/O devices. The system operates to monitor the health of one or more operational characteristics associated with each VM, and in the event that the health of both virtual machines dictates that one or the other of the VMs should be downgraded, but the system is not able to determine which VM should be downgraded and there is an imbalance in a monitored system operational characteristic, the system can defer downgrading one VM for a selected period of time during which the operational characteristic that is in imbalance is monitored. If the imbalance is resolved, the downgrade is cancelled, if an operational fault is confirmed prior to the expiration of the deferral period or if the deferral period expires, then one host is downgraded.
    Type: Application
    Filed: May 5, 2016
    Publication date: November 10, 2016
    Inventors: THOMAS D. BISSETT, STEPHEN J. WARK, PAUL A. LEVEILLE, JAMES D. MCCOLLUM, ANGEL L. PAGAN
  • Publication number: 20090240916
    Abstract: A fault tolerant/fault resilient computer system includes a first coserver and a second coserver. The first coserver includes a first application environment (AE) processor and a first I/O subsystem processor on a first common motherboard. The second coserver includes a second AE processor and a second I/O subsystem processor on a second common motherboard.
    Type: Application
    Filed: May 1, 2009
    Publication date: September 24, 2009
    Applicant: MARATHON TECHNOLOGIES CORPORATION
    Inventors: Glenn A. Tremblay, Paul A. Leveille, James D. McCollum, Thomas D. Bissett, J. Mark Pratt
  • Patent number: 6205565
    Abstract: Data transfer to computing elements is synchronized in a computer system that includes the computing elements and controllers that provide data from data sources to the computing elements. A request for data made by a computing element is intercepted and transmitted to the controllers. At least a first controller responds by transmitting requested data to the computing element and by indicating how a second controller will respond to the intercepted request.
    Type: Grant
    Filed: May 19, 1998
    Date of Patent: March 20, 2001
    Assignee: Marathon Technologies Corporation
    Inventors: Thomas D. Bissett, Martin J. Fitzgerald, V, Paul A. Leveille, James D. McCollum, Erik Muench, Glenn A. Tremblay
  • Patent number: 6038685
    Abstract: In a first aspect, a method of synchronizing at least two computing elements that each have clocks that operate asynchronously of the clocks of the other computing elements includes selecting one or more signals, designated as meta time signals, from a set of signals produced by the computing elements, monitoring the computing elements to detect the production of a selected signal by one of the computing elements, waiting for the other computing elements to produce a selected signal, transmitting equally valued time updates to each of the computing elements, and updating the clocks of the computing elements based on the time updates.In a second aspect, fault resilient or fault tolerant computers are produced by designating a first processor as a computing element, designating a second processor as a controller, connecting the computing element and the controller to produce a modular pair, and connecting at least two modular pairs to produce a fault resilient or fault tolerant computer.
    Type: Grant
    Filed: September 22, 1997
    Date of Patent: March 14, 2000
    Assignee: Marathon Technologies Corporation
    Inventors: Thomas Dale Bissett, Richard D. Fiorentino, Robert M. Glorioso, Diane T. McCauley, James D. McCollum, Glenn A. Tremblay, Mario Troiani
  • Patent number: 5956474
    Abstract: Fault resilient or fault tolerant computers are produced by designating a first processor as a computing element, designating a second processor as a controller, connecting the computing element and the controller to produce a modular pair, and connecting at least two module pairs to produce a fault resilient or fault tolerant computer. Each computing element of the computer performs all instructions in the same number of cycles as the other computing element. The controllers provide input/output processings for the computing elements, as well as monitor their operations to detect errors, and control operation of the computing elements in response to the detected errors.
    Type: Grant
    Filed: December 18, 1996
    Date of Patent: September 21, 1999
    Assignee: Marathon Technologies Corporation
    Inventors: Thomas Dale Bissett, Richard D. Fiorentino, Robert M. Glorioso, Diane T. McCauley, James D. McCollum, Glenn A. Tremblay, Mario Troiani
  • Patent number: 5790397
    Abstract: Data transfer to computing elements is synchronized in a computer system that includes the computing elements and controllers that provide data from data sources to the computing elements. A request for data made by a computing element is intercepted and transmitted to the controllers. At least a first controller responds by transmitting requested data to the computing element and by indicating how a second controller will respond to the intercepted request.
    Type: Grant
    Filed: September 17, 1996
    Date of Patent: August 4, 1998
    Assignee: Marathon Technologies Corporation
    Inventors: Thomas D. Bissett, Martin J. Fitzgerald, V, Paul A. Leveille, James D. McCollum, Erik Muench, Glenn A. Tremblay
  • Patent number: 5615403
    Abstract: The effects of I/O race conditions caused by asynchrony between processors concurrently executing the same software and I/O devices are eliminated by executing an application program and a first associated operating system with firs processors, and executing an I/O processing program and a second associated operating system with an I/O processor. Memory requests from the application program or the first associated operating system are processed with the first processors, and memory requests from the application program to memory addresses associated with I/O devices are trapped and transmitted to the I/O processor. The I/O processor then performs the trapped memory requests with the I/O processing program after waiting for the identical request to be received from each of the first processors to eliminate the effects of race conditions caused by asynchrony between processors concurrently executing the application program or the first associated operating system and I/O devices.
    Type: Grant
    Filed: October 2, 1995
    Date of Patent: March 25, 1997
    Assignee: Marathon Technologies Corporation
    Inventors: Thomas D. Bissett, Richard D. Fiorentino, Robert M. Glorioso, Diane T. McCauley, James D. McCollum, Glenn A. Tremblay, Mario Troiani
  • Patent number: 5600784
    Abstract: In a first aspect, a method of synchronizing at least two computing elements that each have clocks that operate asynchronously of the clocks of the other computing elements includes selecting one or more signals, designated as meta time signals, from a set of signals produced by the computing elements, monitoring the computing elements to detect the production of a selected signal by one of the computing elements, waiting for the other computing elements to produce a selected signal, transmitting equally valued time updates to each of the computing elements, and updating the clocks of the computing elements based on the time updates.In a second aspect, fault resilient or fault tolerant computers are produced by designating a first processor as a computing element, designating a second processor as a controller, connecting the computing element and the controller to produce a modular pair, and connecting at least two modular pairs to produce a fault resilient or fault tolerant computer.
    Type: Grant
    Filed: March 16, 1995
    Date of Patent: February 4, 1997
    Assignee: Marathon Technologies Corporation
    Inventors: Thomas D. Bissett, Richard D. Fiorentino, Robert M. Glorioso, Diane T. McCauley, James D. McCollum, Glenn A. Tremblay
  • Patent number: D642798
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: August 9, 2011
    Inventor: James D. McCollum