Abstract: An electronic dispersion compensation module may perform one or more electronic dispersion compensation solutions. The electronic dispersion compensation module may include a solution control module. The solution control module may configure the electronic dispersion compensation module to perform an electronic dispersion compensation solution using data indicating a bit error rate. A bit error rate module may create the data indicating a bit error rate. The bit error rate module may form part of a clock and data recovery module. The electronic dispersion compensation module may be configured to receive a signal from a backplane and may also be configured to apply any of a plurality of electronic dispersion compensation solutions to the signal received from the backplane.

Abstract: A passive full-duplex bidirectional ZPL tap includes first and second network ports and first and second tap ports. A passive signal separator is configured to receive a data stream from at least one of the first or second network port and pass through the data stream and a first signal portion comprising at least the first signal component and a second signal portion comprising at least the second signal component. A first receive only physical interface device (Phy) is configured to receive the first signal portion from the signal separator and provide the first portion to the first tap port and a second receive only Phy is configured to receive the second signal portion from the signal separator and provide the second signal portion to the second tap port.

Abstract: The principles of the present invention relate to passive full-duplex bidirectional Zero Packet Loss (ZPL) network taps that include single, dual, or dual differential couplers that are placed in the communication path between two network devices that communicate using a full-duplex bidirectional data stream that include a first and a second data component. The bidirectional couplers are configured to at least partially obtain a second data stream that includes at least the first data component and to obtain a third data stream that includes at least the second data component. In some embodiments, the bidirectional couplers may include a signal separation module or stage that is configured to further separate the first and second data components.

Abstract: A receive or listen only Physical Interface Device (Phy). The receive or listen only Phy is configured to have a front end configured to only receive data from a communications network. The receive only Phy may be implemented a part of a tap device including a first network port for receiving a first network signal having a first format; a receive only Phy for converting the first network signal into a second signal format; and a transmit and receive Phy for receiving the first network signal in the second signal format and converting it into the first signal format.

Abstract: The teachings described herein are generally concerned with systems and methods for selectively enabling an electronic device, such as an optical transceiver, that is configured to communicate with a remote computer. In one example of such a method, identification data is initially transmitted from the electronic device to the remote computer. At the remote computer, a determination is made as to whether the identification data is valid. If the identification data is valid, the remote computer generates encrypted data based upon the valid identification data. The encrypted data is then transmitted to the electronic device, where the encrypted data and the identification data are process to facilitate a determination as to whether operation of the electronic device will be enabled. The scope or extent to which the electronic device can be enabled is defined by predetermined criteria.

Abstract: A passive full-duplex bidirectional ZPL tap includes first and second network ports and tap ports. A signal separator is configured to receive a data stream from at least one of the first or second network ports and pass through the data stream and configured to obtain a first signal portion comprising at least the first signal component and obtain a second signal portion comprising at least the second signal component. A DSP stage is configured to substantially remove any second data component from the first signal portion and to substantially remove any first data component from the second signal portion. A first receive only Phy is configured to receive the first signal portion and provide the first signal portion to the first tap port and a second receive only Phy is configured to receive the second signal portion and provide the second signal portion to the second tap port.

Abstract: A network tap device array including one or more passive full-duplex bidirectional ZPL network tap devices is disclosed. The array enables data from multiple nodes in a communications network to be tapped and forwarded to a plurality of monitoring devices. In one embodiment the network tap device array includes a chassis that is configured to receive a plurality of passive full-duplex bidirectional ZPL network tap devices. Each passive full-duplex bidirectional ZPL network tap device includes network ports for passing network data via communication cables and tap ports for forwarding the tapped network data to the monitoring device. In another embodiment, a sub-chassis includes a plurality of passive full-duplex bidirectional ZPL network tap devices and an aggregator that aggregates tapped data from each of the tap devices. The aggregator then forwards the aggregated data to the monitoring device. The sub-chassis can be included in a chassis that is configured to receive multiple populated chassis.

Abstract: An electronic dispersion compensation module may perform one or more electronic dispersion compensation solutions. The electronic dispersion compensation module may include a solution control module. The solution control module may configure the electronic dispersion compensation module to perform an electronic dispersion compensation solution using data indicating a bit error rate. A bit error rate module may create the data indicating a bit error rate. The bit error rate module may form part of a clock and data recovery module. The electronic dispersion compensation module may be configured to receive a signal from a backplane and may also be configured to apply any of a plurality of electronic dispersion compensation solutions to the signal received from the backplane.

Abstract: A test has been developed that is known as the transmitter waveform dispersion penalty (TWDP) test. The TWDP test has been used to test and certify various optical data transmission devices. Similar tests are being developed to test optical receivers such as a difference waveform distortion penalty (dWDP). A test pattern used to generate the transmitted sequence by the device under test is a PRBS9. The PRBS9 test pattern begins with a run of nine ones and has a length of 511 bits. According to the teachings herein, a test pattern of less than 511 bits is generated to perform the TWDP and dWDP tests. The test pattern may include a sequence of bits specifically designed to provide reliable test penalty calculation without the costly and time consuming aspects of the conventional TWDP and dWDP tests using the PRBS9 pattern.

Abstract: Methods and devices provide for a dynamic bias voltage control in detector photodiodes. The methods and systems use a bias control loop to make continuous detections of changes in the effective breakdown current of the detector photodiodes, thereby enabling the devices to change the bias voltage as needed. In one embodiment, a sense diode is added and operated at the breakdown current while the detector diode is operated at a small offset from the breakdown current. As performance conditions change, a feedback loop with the sense diode detects changes in the breakdown current and is used to adjust the bias voltage as necessary. In another embodiment, no sense diode is used. Rather, the detector diode itself is maintained at the breakdown current by a low frequency feedback loop. The optical signal is measured by a high frequency filter.

Abstract: This disclosure is generally concerned with optical transceivers. In one example, an optical transceiver implements electronic dispersion compensation in the receive path, as well as optical preemphasis on the transmitted signal in order to improve aspects of optical performance on multimode fiber links, relative to systems that do not implement transmitter preemphasis. Among other things, such optical transceivers can be used to achieve longer link lengths over a given fiber and/or to improve the percentage of fibers that can be used with a given performance electronic dispersion implementation.

Abstract: A modulation system having in-phase and quadrature phase (IQ) calibration while on-line. The modulation system includes an on-line correction data state detector, an IQ correction code, and a scalar amplitude detector. The on-line correction state detector detects the presence of particular data states that are expected to result in particular modulation states or transition locations. When a particular data state is detected the IQ correction code compares the detected scalar magnitude with others that have been detected. The IQ correction code then uses the comparison to generate adjustments for I and Q offsets, I/Q phase, and I/Q gain. In a rotation embodiment, the modulation system further includes a rotation signal generator for generating rotation angles and an IQ rotator for applying the rotation angles for rotating the I and Q digital data streams.

Abstract: A modulation system having in-phase and quadrature phase (IQ) calibration while on-line. The modulation system includes an on-line correction data state detector, an IQ correction code, and a scalar amplitude detector. The on-line correction state detector detects the presence of particular data states that are expected to result in particular modulation states or transition locations. When a particular data state is detected the IQ correction code compares the detected scalar magnitude with others that have been detected. The IQ correction code then uses the comparison to generate adjustments for I and Q offsets, I/Q phase, and I/Q gain. In a rotation embodiment, the modulation system further includes a rotation signal generator for generating rotation angles and an IQ rotator for applying the rotation angles for rotating the I and Q digital data streams.

Abstract: A modulation system having in-phase and quadrature phase (IQ) calibration while on-line. The modulation system includes digital filters for converting I and Q data bit streams into filtered multilevel I and Q digital data streams, digital-to-analog converters for converting the digital data streams from digital to analog form, and an IQ modulator for converting the analog I and Q data streams into a modulated output signal having a representative IQ diagram having modulation states and transition locations between the modulation states. The digital filters include forward shifting memories having several samples of the data bit streams for each data bit time. The system also includes an on-line correction data state detector, an IQ correction code, and a scalar amplitude detector. The on-line correction state detector monitors the data states in the memory and detects the presence of particular data states that are expected to result in particular modulation states or transition locations.

Abstract: A modulation system having in-phase and quadrature phase (IQ) calibration while on-line. The modulation system includes digital filters for converting I and Q data bit streams into filtered multilevel I and Q digital data streams, digital-to-analog converters, and an IQ modulator for converting the analog I and Q data streams into a modulated output signal having a representative IQ diagram having modulation states and transition locations between the modulation states. The system also includes an on-line correction data state detector, an IQ correction code, and a scalar amplitude detector. The on-line correction state detector monitors the data states in memories of the digital filters and detects the presence of particular data states that are expected to result in particular modulation states or transition locations. The amplitude detector monitors the modulated output signal and provides representative detected magnitudes.

Abstract: A method and apparatus for filtering an undesired ingress signal from an input signal. The apparatus includes an adaptive filter including an ingress synthesizer for recreating the undesired ingress signal and an ingress subtractor for subtracting the recreated ingress signal from the input signal. The ingress synthesizer includes a replica generator for generating replicas corresponding respectively to the input signal symbols, first summers for subtracting the replicas from the input signal for providing respective intermediate signals, second summers for subtracting a recreated ingress signal from the intermediate signals for providing respective error signals, a decision circuit for selecting the intermediate signal corresponding to the error signal having the smallest magnitude, and an ingress generator for processing the selected intermediate signal for providing the recreated ingress signal to the second summers and the ingress subtractor.

Abstract: A tunable digital modulator is tunable across an R.F. frequency range for transmission without additional frequency conversion and includes two toggled multiplexed analog-to-digital converters for reducing spurious frequency components in the output. The modulator and digital-to-analog converters are fabricated in a single integrated circuit with the two converters laid out physically in adjacent spaces with their gain and voltage characteristics matched. By alternating the two digital-to-analog converters in producing the analog modulated signal output, transients from switching of the converters have a chance to die out before the output of each converter is sampled. Thus, any spurious glitch energy is greatly attenuated.

Abstract: Method and apparatus for calibration of a vector modulator of electrical communication signals that produces an output composed of the vector sum of two modulated signals that are phase shifted relative to one another. The two output component signals are first calibrated to produce zero quadrature angle error, then compensated for carrier leakage and balanced to provide equal output amplitudes for equal data input amplitudes. Iteration of these calibrations is not necessary. The already-adjusted parameters remain calibrated as subsequent adjustments of other parameters are made.