Patents by Inventor James D. Pack

James D. Pack has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6778148
    Abstract: A planar sensor array described herein as a spiral lattice planar array is comprised of a plurality of sets of sensor elements wherein for each set of the sensor elements an element is disposed at a vertex of an equilateral non-equiangular pentagon. One embodiment includes a plurality of sets of the pentagon arranged elements in an annular array configuration having a centrally located open center defined by the annular array. Another embodiment includes a plurality of sets of the pentagon arranged elements in a core configuration. The core configuration can be disposed within the open center of the annular array configuration. All sensor elements are confined to a single plane. The sensor elements can be equally weighted or may be weighted to provide side-lobe adjustment.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: August 17, 2004
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: James D. Pack
  • Patent number: 4397029
    Abstract: Equalizer apparatus is provided which includes a number of successively cled lattice stages, each of the stages comprising a selected configuration of adjustable electrical components, the input to the first stage of the successively coupled lattice stages comprising the output of a data transmission channel. The equalizer apparatus further includes a subtractor device coupled to the lattice stages for providing a succession of error terms, each of the error terms comprising an accumulation of the squares of a number of error quantities, each of the error quantities indicating the difference between an undistorted training signal, in a sequence of training signals which are received by the subtractor device, and the same training signal after it has travelled through the data transmission channel and is received by the lattice stages.
    Type: Grant
    Filed: February 17, 1981
    Date of Patent: August 2, 1983
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Edgar H. Satorius, James D. Pack, Mark J. Shensa
  • Patent number: 4375692
    Abstract: An improved equalizer receives the output of a data transmission channel at he first stage of a number of successively coupled lattice stages which are each made up of a selected configuration of adjustable electrical components. A subtractor device is coupled to the lattice stages for providing a succession of error terms. The error terms are an accumulation of the squares of a number of error quantities, which are the differences between a sequence of undistorted training signals or estimates of the transmitted signal which are received by the subtractor device, and the same training signals after they have travelled through the data transmission channel. A delayed stage and two dimensional vector matrices are coupled in each of the lattice stages for iteratively adjusting their components in accordance with a least squares procedure, that is, the components are adjusted each time a signal is received and the iterative adjustment continues until a prespecified error limit is reached.
    Type: Grant
    Filed: April 30, 1981
    Date of Patent: March 1, 1983
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Mark J. Shensa, Edgar H. Satorius, James D. Pack