Patents by Inventor James D. Sansbury
James D. Sansbury has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6828620Abstract: A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.Type: GrantFiled: May 12, 2003Date of Patent: December 7, 2004Assignee: Altera CorporationInventors: Christopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright
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Patent number: 6781883Abstract: Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage.Type: GrantFiled: July 15, 2003Date of Patent: August 24, 2004Assignee: Altera CorporationInventors: Raminda U. Madurawe, Myron W. Wong, John C. Costello, James D. Sansbury, Bruce E. Mielk
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Patent number: 6646919Abstract: Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage.Type: GrantFiled: June 4, 2001Date of Patent: November 11, 2003Assignee: Altera CorporationInventors: Raminda U. Madurawe, Myron W. Wong, John C. Costello, James D. Sansbury, Bruce F. Mielke
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Publication number: 20030197218Abstract: A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.Type: ApplicationFiled: May 12, 2003Publication date: October 23, 2003Applicant: Altera CorporationInventors: Christopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright
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Patent number: 6573138Abstract: A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.Type: GrantFiled: July 8, 1999Date of Patent: June 3, 2003Assignee: Altera CorporationInventors: Christopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright
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Patent number: 6532170Abstract: A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (810). In one embodiment, the programmable memory element (810) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).Type: GrantFiled: August 2, 2001Date of Patent: March 11, 2003Assignee: Altera CorporationInventors: Raminda U. Madurawe, James D. Sansbury
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Patent number: 6456529Abstract: A programmable impedance element (204) is implemented using integrated circuit techniques and devices. An impedance of the programmable impedance element is adjusted by appropriately configuring the element. The programmable impedance element has a range of impedance values, and is configurable to be a value within this range. In an embodiment, the programmable impedance element is implemented using a floating gate device (230), and is nonvolatile.Type: GrantFiled: September 27, 2001Date of Patent: September 24, 2002Assignee: SanDisk CorporationInventors: James D. Sansbury, Sau C. Wang
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Patent number: 6442073Abstract: A nonvolatile memory cell (500) has multiple oxide thicknesses, a tunnel oxide portion (625) and thicker gate oxide portion (630). The memory cell (500) may be used to form compact arrays of memory cells to store logical data. During programming of a selected memory cell, unselected memory cells are not disturbed, and oxide stress for the unselected memory cells is minimized. Techniques for operating programming, erasing, and characterizing the memory cell with multiple oxide thicknesses are discussed.Type: GrantFiled: April 10, 2001Date of Patent: August 27, 2002Assignee: Altera CorporationInventor: James D. Sansbury
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Patent number: 6366498Abstract: A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).Type: GrantFiled: August 30, 1999Date of Patent: April 2, 2002Assignee: Altera CorporationInventors: Raminda U. Madurawe, James D. Sansbury
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Publication number: 20020034098Abstract: A programmable impedance element (204) is implemented using integrated circuit techniques and devices. An impedance of the programmable impedance element is adjusted by appropriately configuring the element. The programmable impedance element has a range of impedance values, and is configurable to be a value within this range. In an embodiment, the programmable impedance element is implemented using a floating gate device (230), and is nonvolatile.Type: ApplicationFiled: September 27, 2001Publication date: March 21, 2002Inventors: James D. Sansbury, Sau C. Wang
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Patent number: 6320788Abstract: A programmable impedance element (204) is implemented using integrated circuit techniques and devices. An impedance of the programmable impedance element is adjusted by appropriately configuring the element. The programmable impedance element has a range of impedance values, and is configurable to be a value within this range. In an embodiment, the programmable impedance element is implemented using a floating gate device (230), and is nonvolatile.Type: GrantFiled: September 11, 2000Date of Patent: November 20, 2001Assignee: Sandisk CorporationInventors: James D. Sansbury, Sau C. Wang
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Patent number: 6295230Abstract: A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).Type: GrantFiled: August 30, 1999Date of Patent: September 25, 2001Assignee: Altera CoporationInventors: Raminda U. Madurawe, James D. Sansbury
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Patent number: 6282122Abstract: Techniques are used to evaluate margin of programmable memory cells. In particular, techniques are used to measure negative erased threshold voltage levels.Type: GrantFiled: December 14, 1999Date of Patent: August 28, 2001Assignee: Altera CorporationInventor: James D. Sansbury
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Patent number: 6268623Abstract: Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage.Type: GrantFiled: December 22, 1997Date of Patent: July 31, 2001Assignee: Altera CorporationInventors: Raminda U. Madurawe, Myron W. Wong, John C. Costello, James D. Sansbury, Bruce E. Mielke
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Patent number: 6243296Abstract: A nonvolatile memory cell (600) has a read device (510), program device (515), and tunnel diode (535). A write control line (WC) is directly coupled to the tunnel diode (535). The memory cell (500) may be used to form compact arrays of memory cells to store logical data. During programming of a selected memory cell, half-select voltages are used on the write control (WC) and control gate lines (CG) for unselected memory cells to prevent disturb and minimize oxide stress.Type: GrantFiled: June 22, 1999Date of Patent: June 5, 2001Assignee: Altera CorporationInventor: James D. Sansbury
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Patent number: 6236597Abstract: A nonvolatile memory cell (500) has multiple oxide thicknesses, a tunnel oxide portion (625) and thicker gate oxide portion (630). The memory cell (500) may be used to form compact arrays of memory cells to store logical data. During programming of a selected memory cell, unselected memory cells are not disturbed, and oxide stress for the unselected memory cells is minimized. Techniques for operating programming, erasing, and characterizing the memory cell with multiple oxide thicknesses are discussed.Type: GrantFiled: March 24, 1998Date of Patent: May 22, 2001Assignee: Altera CorporationInventor: James D. Sansbury
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Patent number: 6226201Abstract: A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).Type: GrantFiled: October 13, 1998Date of Patent: May 1, 2001Assignee: Altera CorporationInventors: Raminda U. Madurawe, James D. Sansbury
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Patent number: 6201734Abstract: A programmable impedance element (204) is implemented using integrated circuit techniques and devices. An impedance of the programmable impedance element is adjusted by appropriately configuring the element. The programmable impedance element has a range of impedance values, and is configurable to be a value within this range. In an embodiment, the programmable impedance element is implemented using a floating gate device (230), and is nonvolatile.Type: GrantFiled: September 25, 1998Date of Patent: March 13, 2001Assignee: SanDisk CorporationInventors: James D. Sansbury, Sau C. Wang
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Patent number: 6122209Abstract: A static, nonvolatile, and reprogrammable programmable interconnect junction cell for implementing programmable interconnect in an integrated circuit. The programmable interconnect junction (600) is programmably configured to couple or decouple a first interconnect line (210) and a second interconnect line (220). The configured state of the programmable interconnect junction is detected directly, and memory cell detection circuitry such as sense amplifiers are not needed during normal operation. Full-rail voltages may be passed from the first interconnect line and the second interconnect line.Type: GrantFiled: July 8, 1999Date of Patent: September 19, 2000Assignee: Altera CorporationInventors: Christopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright
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Patent number: 6078521Abstract: A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).Type: GrantFiled: August 30, 1999Date of Patent: June 20, 2000Assignee: Altera CorporationInventors: Raminda U. Madurawe, James D. Sansbury