Patents by Inventor James D. Sproch
James D. Sproch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10741538Abstract: In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.Type: GrantFiled: July 28, 2017Date of Patent: August 11, 2020Assignee: Synopsys, Inc.Inventors: Victor Moroz, Jamil Kawa, James D. Sproch, Robert B. Lefferts
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Publication number: 20170330872Abstract: In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.Type: ApplicationFiled: July 28, 2017Publication date: November 16, 2017Applicant: Synopsys, Inc.Inventors: Victor Moroz, Jamil Kawa, James D. Sproch, Robert B. Lefferts
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Patent number: 9728528Abstract: In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.Type: GrantFiled: December 9, 2014Date of Patent: August 8, 2017Assignee: SYNOPSYS, INC.Inventors: Victor Moroz, Jamil Kawa, James D. Sproch, Robert B. Lefferts
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Patent number: 9287253Abstract: In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.Type: GrantFiled: December 22, 2011Date of Patent: March 15, 2016Assignee: Synopsys, Inc.Inventors: Victor Moroz, Jamil Kawa, James D. Sproch, Robert B. Lefferts
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Publication number: 20150162320Abstract: In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.Type: ApplicationFiled: December 9, 2014Publication date: June 11, 2015Applicant: SYNOPSYS, INC.Inventors: Victor Moroz, Jamil Kawa, James D. Sproch, Robert B. Lefferts
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Patent number: 8999766Abstract: Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone.Type: GrantFiled: December 18, 2013Date of Patent: April 7, 2015Assignee: Synopsys, Inc.Inventors: Qing Su, Min Ni, Zongwu Tang, Jamil Kawa, James D. Sproch
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Patent number: 8877638Abstract: Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone.Type: GrantFiled: August 6, 2012Date of Patent: November 4, 2014Assignee: Synopsys, Inc.Inventors: Jamil Kawa, Min Ni, James D. Sproch, Qing Su, Zongwu Tang
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Publication number: 20140109027Abstract: Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone.Type: ApplicationFiled: December 18, 2013Publication date: April 17, 2014Applicant: SYNOPSYS, INC.Inventors: Qing Su Su, Min Ni Ni, Zongwu Tang, Jamil Kawa, James D. Sproch
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Publication number: 20130113547Abstract: In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.Type: ApplicationFiled: December 22, 2011Publication date: May 9, 2013Applicant: Synopsys. Inc.Inventors: Victor Moroz, Jamil Kawa, James D. Sproch, Robert B. Lefferts
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Publication number: 20130026575Abstract: Roughly described, an integrated circuit device has formed on a substrate a plurality of transistors including a first subset of at least one transistor and a second subset of at least one transistor, wherein all of the transistors in the first subset have one underlap distance and all of the transistors in the second subset have a different underlap distance. The transistors in the first and second subsets preferably have different threshold voltages, and preferably realize different points on the high performance/low power tradeoff.Type: ApplicationFiled: July 28, 2011Publication date: January 31, 2013Applicant: SYNOPSYS, INC.Inventors: Victor Moroz, James D. Sproch
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Publication number: 20120295433Abstract: Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone.Type: ApplicationFiled: August 6, 2012Publication date: November 22, 2012Applicant: SYNOPSYS, INC.Inventors: Qing Su, Min Ni, Zongwu Tang, Jamil Kawa, James D. Sproch
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Patent number: 8264065Abstract: Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone.Type: GrantFiled: October 23, 2009Date of Patent: September 11, 2012Assignee: Synopsys, Inc.Inventors: Qing Su, Min Ni, Zongwu Tang, Jamil Kawa, James D. Sproch
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Publication number: 20110095367Abstract: Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone.Type: ApplicationFiled: October 23, 2009Publication date: April 28, 2011Applicant: SYNOPSYS, INC.Inventors: Qing Su, Min Ni, Zongwu Tang, Jamil Kawa, James D. Sproch
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Patent number: 6247134Abstract: A method and system for power savings within a pipelined design by performing intelligent stage gating. The present invention recognizes that not every operand applied to the input of a pipeline requires a recomputation in the different pipeline stages. Circuitry is used to generate a signal, C, indicating that this condition holds. C is then used to gate the register bank at the input of the first pipeline stage thereby potentially saving power in the register bank. Moreover, C can also be stored in a register, the output of which: a) gates the register bank of the second stage; and b) connects to another register to store signal C to be used in the third stage. Power savings is provided by not clocking the register circuit of the stage, and in some instances, power is saved within the stage's associated combinational logic. In one embodiment, a register (to store C) is added in each stage of a pipeline to use C as a gating signal in the subsequent stage.Type: GrantFiled: March 31, 1999Date of Patent: June 12, 2001Assignee: Synopsys, Inc.Inventors: James D. Sproch, Michael Münch, Renu Mehra
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Patent number: 4719456Abstract: A video dot intensity balancer for use in a video display system wherein information is represented by a series of logic bits in a video stream corresponding to dots to be displayed on a CRT is disclosed. Logic elements are coupled to the output of a bit generator for comparing adjacent bits and outputting an information-defining signal wherein a single information-defining bit never stands alone. In this manner, apparent intensity imbalances on the video screen are eliminated.Type: GrantFiled: March 8, 1985Date of Patent: January 12, 1988Assignee: Standard Microsystems CorporationInventors: James D. Sproch, Morton B. Herman
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Patent number: 4638459Abstract: A dynamic read only memory (ROM) which comprises a memory select precharge section, a memory select section, a memory section, a memory precharge section and a plurality of grounding devices. The ground reference for the pulldown transistors is selectively activated at an appropriate time such that the memory sections are active only for a relatively brief portion of the memory cycle, thereby reducing dc power consumption and simplifying the driver circuit.Type: GrantFiled: January 31, 1985Date of Patent: January 20, 1987Assignee: Standard Microsystems Corp.Inventors: Henry W. Pechar, Jr., James D. Sproch